ARM: dts: imx: Add the missing cpus node

To make it consistent with the other i.mx SoCs, let's add the cpus nodes.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index a69abaa87a2680dd3996c0c48f840efecbd60919..bcd317172c0d89d8974d42e553d5db6a56f11b47 100644 (file)
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -32,6 +32,16 @@
                usb1 = &usbhost1;
        };
 
+       cpus {
+               #address-cells = <0>;
+               #size-cells = <0>;
+
+               cpu {
+                       compatible = "arm,arm926ej-s";
+                       device_type = "cpu";
+               };
+       };
+
        asic: asic-interrupt-controller@68000000 {
                compatible = "fsl,imx25-asic", "fsl,avic";
                interrupt-controller;

diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 81167787785f294191c657fb9d5dc2ff7c078c49..c34f82581248a98f1b3a83da99fa50eda502a42c 100644 (file)
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -20,6 +20,16 @@
                serial4 = &uart5;
        };
 
+       cpus {
+               #address-cells = <0>;
+               #size-cells = <0>;
+
+               cpu {
+                       compatible = "arm,arm1136";
+                       device_type = "cpu";
+               };
+       };
+
        avic: avic-interrupt-controller@60000000 {
                compatible = "fsl,imx31-avic", "fsl,avic";
                interrupt-controller;

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a2115fa7c373deb98ba70047813d3045a4cb629a..faceb22f2f6562b6c9aa553de8cdea241ea7b4b3 100644 (file)
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -35,6 +35,16 @@
                spi2 = &cspi;
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a8";
+                       reg = <0x0>;
+               };
+       };
+
        tzic: tz-interrupt-controller@0fffc000 {
                compatible = "fsl,imx53-tzic", "fsl,tzic";
                interrupt-controller;