/* Basic 'timer condition met' check */
        __GUEST_ASSERT(xcnt >= cval,
-                      "xcnt = 0x%llx, cval = 0x%llx, xcnt_diff_us = 0x%llx",
+                      "xcnt = 0x%lx, cval = 0x%lx, xcnt_diff_us = 0x%lx",
                       xcnt, cval, xcnt_diff_us);
-       __GUEST_ASSERT(xctl & CTL_ISTATUS, "xcnt = 0x%llx", xcnt);
+       __GUEST_ASSERT(xctl & CTL_ISTATUS, "xcnt = 0x%lx", xcnt);
 
        WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1);
 }
 
                case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
                case TEST_STAGE_HVC_IFACE_FALSE_INFO:
                        __GUEST_ASSERT(res.a0 == SMCCC_RET_NOT_SUPPORTED,
-                                      "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%llx, stage = %u",
+                                      "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%lx, stage = %u",
                                        res.a0, hc_info->func_id, hc_info->arg1, stage);
                        break;
                case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
                        __GUEST_ASSERT(res.a0 != SMCCC_RET_NOT_SUPPORTED,
-                                      "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%llx, stage = %u",
+                                      "a0 = 0x%lx, func_id = 0x%x, arg1 = 0x%lx, stage = %u",
                                        res.a0, hc_info->func_id, hc_info->arg1, stage);
                        break;
                default:
 
                                                                                 \
        if (set_expected)                                                        \
                __GUEST_ASSERT((_tval & mask),                                   \
-                               "tval: 0x%lx; mask: 0x%lx; set_expected: 0x%lx", \
+                               "tval: 0x%lx; mask: 0x%lx; set_expected: %u",    \
                                _tval, mask, set_expected);                      \
        else                                                                     \
                __GUEST_ASSERT(!(_tval & mask),                                  \
-                               "tval: 0x%lx; mask: 0x%lx; set_expected: 0x%lx", \
+                               "tval: 0x%lx; mask: 0x%lx; set_expected: %u",    \
                                _tval, mask, set_expected);                      \
 }
 
        acc->write_typer(pmc_idx, write_data);
        read_data = acc->read_typer(pmc_idx);
        __GUEST_ASSERT(read_data == write_data,
-                      "pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
+                      "pmc_idx: 0x%x; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
                       pmc_idx, PMC_ACC_TO_IDX(acc), read_data, write_data);
 
        /*
 
        /* The count value must be 0, as it is disabled and reset */
        __GUEST_ASSERT(read_data == 0,
-                      "pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx",
+                      "pmc_idx: 0x%x; acc_idx: 0x%lx; read_data: 0x%lx",
                       pmc_idx, PMC_ACC_TO_IDX(acc), read_data);
 
        write_data = read_data + pmc_idx + 0x12345;
        acc->write_cntr(pmc_idx, write_data);
        read_data = acc->read_cntr(pmc_idx);
        __GUEST_ASSERT(read_data == write_data,
-                      "pmc_idx: 0x%lx; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
+                      "pmc_idx: 0x%x; acc_idx: 0x%lx; read_data: 0x%lx; write_data: 0x%lx",
                       pmc_idx, PMC_ACC_TO_IDX(acc), read_data, write_data);
 }
 
        int i, pmc;
 
        __GUEST_ASSERT(expected_pmcr_n <= ARMV8_PMU_MAX_GENERAL_COUNTERS,
-                       "Expected PMCR.N: 0x%lx; ARMv8 general counters: 0x%lx",
+                       "Expected PMCR.N: 0x%lx; ARMv8 general counters: 0x%x",
                        expected_pmcr_n, ARMV8_PMU_MAX_GENERAL_COUNTERS);
 
        pmcr = read_sysreg(pmcr_el0);