drm/amdgpu: set CPU mapping of vram as cached for A+A mode

New A+A HW supports cached vram mapped to cpu.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0ea1b68e7bb9fcca2afb92893ff3b7c38e0b2d1d..c5fea144b759d5db0677fb37c337f5dfa241de0f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
 
                mem->bus.offset += adev->gmc.aper_base;
                mem->bus.is_iomem = true;
-               mem->bus.caching = ttm_write_combined;
+               if (adev->gmc.xgmi.connected_to_cpu)
+                       mem->bus.caching = ttm_cached;
+               else
+                       mem->bus.caching = ttm_write_combined;
                break;
        default:
                return -EINVAL;