drm/amd/display: log destination of vertical interrupt

[Why]
Knowing the destination of OTG's vertical interrupt 2 is useful for
debugging, but it is not currently included in the OTG state readback
logic

[How]
Read the OTG interrupt destination register to get the vertical interrupt
2 destination on ASICs that have this register when reading back the OTG
state from hardware

Reviewed-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 88cf47a5ea751869270061906cc687fbd5ae7fbc..baf663b661c849b5e8231198a8308ce9b2d09494 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -429,7 +429,9 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
                struct dcn_otg_state s = {0};
                int pix_clk = 0;
 
-               optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+               if (tg->funcs->read_otg_state)
+                       tg->funcs->read_otg_state(tg, &s);
+
                pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 
                //only print if OTG master is enabled
@@ -495,7 +497,8 @@ static void dcn10_clear_otpc_underflow(struct dc *dc)
                struct timing_generator *tg = pool->timing_generators[i];
                struct dcn_otg_state s = {0};
 
-               optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+               if (tg->funcs->read_otg_state)
+                       tg->funcs->read_otg_state(tg, &s);
 
                if (s.otg_enabled & 1)
                        tg->funcs->clear_optc_underflow(tg);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 44e405e9bc971544f3aa0b9f460cb3ed9e65e818..c3cf2706b6ba55cc3c845b019b4a53755f667ada 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -415,7 +415,8 @@ void dcn10_log_hw_state(struct dc *dc,
                struct timing_generator *tg = pool->timing_generators[i];
                struct dcn_otg_state s = {0};
                /* Read shared OTG state registers for all DCNx */
-               optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+               if (tg->funcs->read_otg_state)
+                       tg->funcs->read_otg_state(tg, &s);
 
                /*
                 * For DCN2 and greater, a register on the OPP is used to

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
index 6fdc9809280ca2db60fec4f16c8b67149711a2ba..7f371cbb35cdef1c5ef5443af03d1e162904191e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
@@ -70,35 +70,7 @@ struct optc {
        enum signal_type signal;
 };
 
-struct dcn_otg_state {
-       uint32_t v_blank_start;
-       uint32_t v_blank_end;
-       uint32_t v_sync_a_pol;
-       uint32_t v_total;
-       uint32_t v_total_max;
-       uint32_t v_total_min;
-       uint32_t v_total_min_sel;
-       uint32_t v_total_max_sel;
-       uint32_t v_sync_a_start;
-       uint32_t v_sync_a_end;
-       uint32_t h_blank_start;
-       uint32_t h_blank_end;
-       uint32_t h_sync_a_start;
-       uint32_t h_sync_a_end;
-       uint32_t h_sync_a_pol;
-       uint32_t h_total;
-       uint32_t underflow_occurred_status;
-       uint32_t otg_enabled;
-       uint32_t blank_enabled;
-       uint32_t vertical_interrupt1_en;
-       uint32_t vertical_interrupt1_line;
-       uint32_t vertical_interrupt2_en;
-       uint32_t vertical_interrupt2_line;
-       uint32_t otg_master_update_lock;
-       uint32_t otg_double_buffer_control;
-};
-
-void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);
+void optc1_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s);
 
 bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 9885cb3c310f4f00b7dc3c82beacc1a0d3ce1ccc..267ace4eef8a364b70dc1c5375b3b330237ff42c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -146,6 +146,35 @@ struct crc_params {
        bool reset;
 };
 
+struct dcn_otg_state {
+       uint32_t v_blank_start;
+       uint32_t v_blank_end;
+       uint32_t v_sync_a_pol;
+       uint32_t v_total;
+       uint32_t v_total_max;
+       uint32_t v_total_min;
+       uint32_t v_total_min_sel;
+       uint32_t v_total_max_sel;
+       uint32_t v_sync_a_start;
+       uint32_t v_sync_a_end;
+       uint32_t h_blank_start;
+       uint32_t h_blank_end;
+       uint32_t h_sync_a_start;
+       uint32_t h_sync_a_end;
+       uint32_t h_sync_a_pol;
+       uint32_t h_total;
+       uint32_t underflow_occurred_status;
+       uint32_t otg_enabled;
+       uint32_t blank_enabled;
+       uint32_t vertical_interrupt1_en;
+       uint32_t vertical_interrupt1_line;
+       uint32_t vertical_interrupt2_en;
+       uint32_t vertical_interrupt2_line;
+       uint32_t vertical_interrupt2_dest;
+       uint32_t otg_master_update_lock;
+       uint32_t otg_double_buffer_control;
+};
+
 /**
  * struct timing_generator - Entry point to Output Timing Generator feature.
  */
@@ -350,6 +379,7 @@ struct timing_generator_funcs {
        bool (*get_pipe_update_pending)(struct timing_generator *tg);
        void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);
        bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
+       void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s);
 };
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
index 19d5ebc6763c4a27fc7c98f8adece01bd3e3e0f0..6f7b0f816f2a89f096a6f158ed1857f22480846f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
@@ -1312,7 +1312,7 @@ bool optc1_get_hw_timing(struct timing_generator *tg,
        if (tg == NULL || hw_crtc_timing == NULL)
                return false;
 
-       optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+       optc1_read_otg_state(tg, &s);
 
        hw_crtc_timing->h_total = s.h_total + 1;
        hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
@@ -1328,9 +1328,11 @@ bool optc1_get_hw_timing(struct timing_generator *tg,
 }
 
 
-void optc1_read_otg_state(struct optc *optc1,
+void optc1_read_otg_state(struct timing_generator *optc,
                struct dcn_otg_state *s)
 {
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
        REG_GET(OTG_CONTROL,
                        OTG_MASTER_EN, &s->otg_enabled);
 
@@ -1663,6 +1665,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
                .setup_manual_trigger = optc1_setup_manual_trigger,
                .get_hw_timing = optc1_get_hw_timing,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc1_read_otg_state,
 };
 
 void dcn10_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
index 159172178d51c1e32a8c403b92c0871b008def15..82b91b9bc9c246be385e5f7396e6e6923eb4461e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
@@ -209,6 +209,7 @@ struct dcn_optc_registers {
        uint32_t OPTC_WIDTH_CONTROL2;
        uint32_t OTG_PSTATE_REGISTER;
        uint32_t OTG_PIPE_UPDATE_STATUS;
+       uint32_t INTERRUPT_DEST;
 };
 
 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -591,6 +592,7 @@ struct dcn_optc_registers {
        type OTG_DC_REG_UPDATE_PENDING;\
        type OTG_CURSOR_UPDATE_PENDING;\
        type OTG_VUPDATE_KEEPOUT_STATUS;\
+       type OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST;
 
 #define TG_REG_FIELD_LIST_DCN3_2(type) \
        type OTG_H_TIMING_DIV_MODE_MANUAL;

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
index b4694985a40a42d08d4140a694df77f245278105..81857ce6d68d71b83281b29f77a0324bcda5f80f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
@@ -562,6 +562,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
                .get_hw_timing = optc1_get_hw_timing,
                .align_vblanks = optc2_align_vblanks,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc1_read_otg_state,
 };
 
 void dcn20_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
index 49c2efdfa403aed81fa7c8e794521246757c993e..f2415eebdc099901be0f8608e536f5138742eb1f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
@@ -180,6 +180,7 @@ static struct timing_generator_funcs dcn201_tg_funcs = {
                .setup_manual_trigger = optc2_setup_manual_trigger,
                .get_hw_timing = optc1_get_hw_timing,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc1_read_otg_state,
 };
 
 void dcn201_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
index 4c95c095861229de8c4d227abbed488b755af510..78b58a449fa4de7e5add54b63258b949d40926a9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
@@ -420,6 +420,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
                .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,
                .get_otg_double_buffer_pending = optc3_get_otg_update_pending,
                .get_pipe_update_pending = optc3_get_pipe_update_pending,
+               .read_otg_state = optc1_read_otg_state,
 };
 
 void dcn30_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
index d7a45ef2d01b383b767a22ee55d7f651d0821741..65e9089b7f31cb528b110f6d8d8198b44ff2df17 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
@@ -172,6 +172,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
                .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,
                .get_otg_double_buffer_pending = optc3_get_otg_update_pending,
                .get_pipe_update_pending = optc3_get_pipe_update_pending,
+               .read_otg_state = optc1_read_otg_state,
 };
 
 void dcn301_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
index 4b6446ed4ce471a0c762f4baefbc238b987a25ae..ef536f37b4ed8a42ed3477cebd16ab3c3d8a1ba7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
@@ -245,6 +245,76 @@ void optc3_init_odm(struct timing_generator *optc)
        optc1->opp_count = 1;
 }
 
+void optc31_read_otg_state(struct timing_generator *optc,
+               struct dcn_otg_state *s)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+       REG_GET(OTG_CONTROL,
+                       OTG_MASTER_EN, &s->otg_enabled);
+
+       REG_GET_2(OTG_V_BLANK_START_END,
+                       OTG_V_BLANK_START, &s->v_blank_start,
+                       OTG_V_BLANK_END, &s->v_blank_end);
+
+       REG_GET(OTG_V_SYNC_A_CNTL,
+                       OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
+
+       REG_GET(OTG_V_TOTAL,
+                       OTG_V_TOTAL, &s->v_total);
+
+       REG_GET(OTG_V_TOTAL_MAX,
+                       OTG_V_TOTAL_MAX, &s->v_total_max);
+
+       REG_GET(OTG_V_TOTAL_MIN,
+                       OTG_V_TOTAL_MIN, &s->v_total_min);
+
+       REG_GET(OTG_V_TOTAL_CONTROL,
+                       OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
+
+       REG_GET(OTG_V_TOTAL_CONTROL,
+                       OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
+
+       REG_GET_2(OTG_V_SYNC_A,
+                       OTG_V_SYNC_A_START, &s->v_sync_a_start,
+                       OTG_V_SYNC_A_END, &s->v_sync_a_end);
+
+       REG_GET_2(OTG_H_BLANK_START_END,
+                       OTG_H_BLANK_START, &s->h_blank_start,
+                       OTG_H_BLANK_END, &s->h_blank_end);
+
+       REG_GET_2(OTG_H_SYNC_A,
+                       OTG_H_SYNC_A_START, &s->h_sync_a_start,
+                       OTG_H_SYNC_A_END, &s->h_sync_a_end);
+
+       REG_GET(OTG_H_SYNC_A_CNTL,
+                       OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
+
+       REG_GET(OTG_H_TOTAL,
+                       OTG_H_TOTAL, &s->h_total);
+
+       REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
+                       OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
+                       OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
+                               OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
+                       OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
+
+       REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
+                       OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
+
+       REG_GET(INTERRUPT_DEST,
+                       OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, &s->vertical_interrupt2_dest);
+
+       s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
+       s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
+}
+
 static struct timing_generator_funcs dcn31_tg_funcs = {
                .validate_timing = optc1_validate_timing,
                .program_timing = optc1_program_timing,
@@ -306,6 +376,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
                .get_hw_timing = optc1_get_hw_timing,
                .init_odm = optc3_init_odm,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc31_read_otg_state,
 };
 
 void dcn31_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
index fbbe86d00c2e3e0183fd05b27629201af764fc7d..0f72c274f40bb9c64458751e6c62135205f19ac7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h
@@ -100,7 +100,8 @@
        SRI(OTG_CRC_CNTL2, OTG, inst),\
        SR(DWB_SOURCE_SELECT),\
        SRI(OTG_DRR_CONTROL, OTG, inst),\
-       SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
+       SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
+       SRI(INTERRUPT_DEST, OTG, inst)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
        SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -260,6 +261,7 @@
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
+       SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
 
 void dcn31_timing_generator_init(struct optc *optc1);
 
@@ -269,4 +271,7 @@ void optc31_set_drr(struct timing_generator *optc, const struct drr_params *para
 
 void optc3_init_odm(struct timing_generator *optc);
 
+void optc31_read_otg_state(struct timing_generator *optc,
+               struct dcn_otg_state *s);
+
 #endif /* __DC_OPTC_DCN31_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
index 633d62addd4d27b2527cb9a40c734ad9dfe3be93..0e603bad0d1228d71c63d39f3c3aa0d94536f672 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
@@ -255,6 +255,7 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
                .set_odm_combine = optc314_set_odm_combine,
                .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc31_read_otg_state,
 };
 
 void dcn314_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
index 0ff72b97b465c593f742a8eea1c506f556b16b7c..6bfdee3fcf5f7f9950e7851036b606058a6c6240 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h
@@ -99,7 +99,8 @@
        SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
        SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
        SRI(OTG_DRR_CONTROL, OTG, inst),\
-       SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)
+       SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
+       SRI(INTERRUPT_DEST, OTG, inst)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\
        SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
@@ -254,6 +255,7 @@
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
+       SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
 
 void dcn314_timing_generator_init(struct optc *optc1);
 

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index c217f653b3c815544d4078484f32b269fbd4e4ef..2cdd19ba634ba329aaf25e006d331cec23352052 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -364,6 +364,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
                .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,
                .get_otg_double_buffer_pending = optc3_get_otg_update_pending,
                .get_pipe_update_pending = optc3_get_pipe_update_pending,
+               .read_otg_state = optc31_read_otg_state,
 };
 
 void dcn32_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
index 0b0964a9da7487ae17178a794ada09af78890b01..d159e3ed3bb3c7dccae491060cefe58502f59fc1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h
@@ -181,7 +181,8 @@
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh)
+       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
+       SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
 
 void dcn32_timing_generator_init(struct optc *optc1);
 void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index d21e82b927d00c680ddf52c65f70baefe0efbc5e..b86fe2b094f8164b6b7b401a65db97191d78b463 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -492,6 +492,7 @@ static struct timing_generator_funcs dcn35_tg_funcs = {
                .init_odm = optc3_init_odm,
                .set_long_vtotal = optc35_set_long_vtotal,
                .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
+               .read_otg_state = optc31_read_otg_state,
 };
 
 void dcn35_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
index be749ab41dce795b56fa30ba95b2d851844eb176..733a2f149d9a9236d07e36cd09fbda51bedb9dfa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h
@@ -71,7 +71,8 @@
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh)
+       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
+       SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
 
 void dcn35_timing_generator_init(struct optc *optc1);
 

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index 338a0cad23a52364e3811213c5a5e1fe033fb232..bf921d1f500badddb2fc399cb1d21b3740d90aa2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -527,6 +527,7 @@ static struct timing_generator_funcs dcn401_tg_funcs = {
                .get_pipe_update_pending = optc3_get_pipe_update_pending,
                .set_vupdate_keepout = optc401_set_vupdate_keepout,
                .wait_update_lock_status = optc401_wait_update_lock_status,
+               .read_otg_state = optc31_read_otg_state,
 };
 
 void dcn401_timing_generator_init(struct optc *optc1)

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
index 1be89571986fff82f1a6d51dd3707b42f8c747dc..69ad21084fbbdcb5f343fee4c734331cdc1ee9ef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h
@@ -163,7 +163,8 @@
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\
        SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\
-       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh)
+       SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\
+       SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)
 
 void dcn401_timing_generator_init(struct optc *optc1);
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
index 86c6e5e8c42eb870f93a1d0ac688d12c0224afb0..1aa4ced29291ab524a1c88d026a13d073ff2a988 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
@@ -1055,7 +1055,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned
       SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \
       SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
       SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \
-         SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst)
+      SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),                              \
+      SRI_ARR(INTERRUPT_DEST, OTG, inst)
 
 /* HUBP */
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
index 9d03a55d90cf0341d39fa1460350df7008655eee..9c56ae76e0c793ba351c482c3af6ae86a7d5faea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
@@ -305,7 +305,8 @@ struct resource_pool *dcn35_create_resource_pool(
        SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\
        SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\
        SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\
-       SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst)
+       SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
+       SRI_ARR(INTERRUPT_DEST, OTG, inst)
 
 /* DPP */
 #define DPP_REG_LIST_DCN35_RI(id)\

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 19568c359669421d6df34810f17e776f13a67389..4c259745d5190e3db8c34e0d61191d9961839988 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -538,7 +538,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
        SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \
        SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \
        SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst),                                 \
-       SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst)
+       SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),                              \
+       SRI_ARR(INTERRUPT_DEST, OTG, inst)
 
 /* HUBBUB */
 #define HUBBUB_REG_LIST_DCN4_01_RI(id)                                       \