io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
                cmd_completion.cq_interrupt_unmask_register_offset);
 
-       if (cmd_completion.cq_head_db_register_offset)
-               io_cq->cq_head_db_reg =
-                       (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
-                       cmd_completion.cq_head_db_register_offset);
-
        if (cmd_completion.numa_node_register_offset)
                io_cq->numa_node_cfg_reg =
                        (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
 
        /* Interrupt unmask register */
        u32 __iomem *unmask_reg;
 
-       /* The completion queue head doorbell register */
-       u32 __iomem *cq_head_db_reg;
-
        /* numa configuration register (for TPH) */
        u32 __iomem *numa_node_cfg_reg;
 
        /* The value to write to the above register to unmask
         * the interrupt of this queue
         */
-       u32 msix_vector;
+       u32 msix_vector ____cacheline_aligned;
 
        enum queue_direction direction;
 
        /* Device queue index */
        u16 idx;
        u16 head;
-       u16 last_head_update;
        u8 phase;
        u8 cdesc_entry_size_in_bytes;
 
 
 
 #include "ena_com.h"
 
-/* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */
-#define ENA_COMP_HEAD_THRESH 4
 /* we allow 2 DMA descriptors per LLQ entry */
 #define ENA_LLQ_ENTRY_DESC_CHUNK_SIZE  (2 * sizeof(struct ena_eth_io_tx_desc))
 #define ENA_LLQ_HEADER         (128UL - ENA_LLQ_ENTRY_DESC_CHUNK_SIZE)
        return 0;
 }
 
-static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
-{
-       u16 unreported_comp, head;
-       bool need_update;
-
-       if (unlikely(io_cq->cq_head_db_reg)) {
-               head = io_cq->head;
-               unreported_comp = head - io_cq->last_head_update;
-               need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
-
-               if (unlikely(need_update)) {
-                       netdev_dbg(ena_com_io_cq_to_ena_dev(io_cq)->net_device,
-                                  "Write completion queue doorbell for queue %d: head: %d\n",
-                                  io_cq->qid, head);
-                       writel(head, io_cq->cq_head_db_reg);
-                       io_cq->last_head_update = head;
-               }
-       }
-
-       return 0;
-}
-
 static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
                                            u8 numa_node)
 {
 
 
        tx_ring->next_to_clean = next_to_clean;
        ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
-       ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
 
        netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
 
                      ENA_RX_REFILL_THRESH_PACKET);
 
        /* Optimization, try to batch new rx buffers */
-       if (refill_required > refill_threshold) {
-               ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
+       if (refill_required > refill_threshold)
                ena_refill_rx_bufs(rx_ring, refill_required);
-       }
 
        if (xdp_flags & ENA_XDP_REDIRECT)
                xdp_do_flush();
 
 
        tx_ring->next_to_clean = next_to_clean;
        ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
-       ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
 
        netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
                  "tx_poll: q %d done. total pkts: %d\n",