]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
ethtool: Add support for 100Gbps per lane link modes
authorMeir Lichtinger <meirl@mellanox.com>
Tue, 7 Jul 2020 03:42:32 +0000 (20:42 -0700)
committerDavid S. Miller <davem@davemloft.net>
Wed, 8 Jul 2020 22:30:42 +0000 (15:30 -0700)
Define 100G, 200G and 400G link modes using 100Gbps per lane

LR, ER and FR are defined as a single link mode because they are
using same technology and by design are fully interoperable.
EEPROM content indicates if the module is LR, ER, or FR, and the
user space ethtool decoder is planned to support decoding these
modes in the EEPROM.

Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
CC: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Aya Levin <ayal@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/phy/phy-core.c
include/uapi/linux/ethtool.h
net/ethtool/common.c
net/ethtool/linkmodes.c

index 46bd68e9ecfae44d631cf15cb4856e683c948782..ff8e14b01eeb3e9ea8c6872124f3a336ef081c5c 100644 (file)
@@ -8,7 +8,7 @@
 
 const char *phy_speed_to_str(int speed)
 {
-       BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
+       BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
                "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
                "If a speed or mode has been added please update phy_speed_to_str "
                "and the PHY settings array.\n");
@@ -78,12 +78,22 @@ static const struct phy_setting settings[] = {
        PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full   ),
        PHY_SETTING( 400000, FULL, 400000baseDR8_Full           ),
        PHY_SETTING( 400000, FULL, 400000baseSR8_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseCR4_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseKR4_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full   ),
+       PHY_SETTING( 400000, FULL, 400000baseDR4_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseSR4_Full           ),
        /* 200G */
        PHY_SETTING( 200000, FULL, 200000baseCR4_Full           ),
        PHY_SETTING( 200000, FULL, 200000baseKR4_Full           ),
        PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full   ),
        PHY_SETTING( 200000, FULL, 200000baseDR4_Full           ),
        PHY_SETTING( 200000, FULL, 200000baseSR4_Full           ),
+       PHY_SETTING( 200000, FULL, 200000baseCR2_Full           ),
+       PHY_SETTING( 200000, FULL, 200000baseKR2_Full           ),
+       PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full   ),
+       PHY_SETTING( 200000, FULL, 200000baseDR2_Full           ),
+       PHY_SETTING( 200000, FULL, 200000baseSR2_Full           ),
        /* 100G */
        PHY_SETTING( 100000, FULL, 100000baseCR4_Full           ),
        PHY_SETTING( 100000, FULL, 100000baseKR4_Full           ),
@@ -94,6 +104,11 @@ static const struct phy_setting settings[] = {
        PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full   ),
        PHY_SETTING( 100000, FULL, 100000baseDR2_Full           ),
        PHY_SETTING( 100000, FULL, 100000baseSR2_Full           ),
+       PHY_SETTING( 100000, FULL, 100000baseCR_Full            ),
+       PHY_SETTING( 100000, FULL, 100000baseKR_Full            ),
+       PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full      ),
+       PHY_SETTING( 100000, FULL, 100000baseDR_Full            ),
+       PHY_SETTING( 100000, FULL, 100000baseSR_Full            ),
        /* 56G */
        PHY_SETTING(  56000, FULL,  56000baseCR4_Full           ),
        PHY_SETTING(  56000, FULL,  56000baseKR4_Full           ),
index d1413538ef30570e7e0922a6a3bc1b611b4282c2..60856e0f9618b636fdc36a93b49d87363149c4ab 100644 (file)
@@ -1600,6 +1600,21 @@ enum ethtool_link_mode_bit_indices {
        ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT         = 72,
        ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT         = 73,
        ETHTOOL_LINK_MODE_FEC_LLRS_BIT                   = 74,
+       ETHTOOL_LINK_MODE_100000baseKR_Full_BIT          = 75,
+       ETHTOOL_LINK_MODE_100000baseSR_Full_BIT          = 76,
+       ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT    = 77,
+       ETHTOOL_LINK_MODE_100000baseCR_Full_BIT          = 78,
+       ETHTOOL_LINK_MODE_100000baseDR_Full_BIT          = 79,
+       ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT         = 80,
+       ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT         = 81,
+       ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,
+       ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT         = 83,
+       ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT         = 84,
+       ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT         = 85,
+       ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT         = 86,
+       ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,
+       ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT         = 88,
+       ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT         = 89,
        /* must be last entry */
        __ETHTOOL_LINK_MODE_MASK_NBITS
 };
index ce4dbae5a943c0452eed131590e66c8c66ec363a..c541667137970be867fda45436341c40901bf853 100644 (file)
@@ -176,6 +176,21 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
        __DEFINE_LINK_MODE_NAME(400000, DR8, Full),
        __DEFINE_LINK_MODE_NAME(400000, CR8, Full),
        __DEFINE_SPECIAL_MODE_NAME(FEC_LLRS, "LLRS"),
+       __DEFINE_LINK_MODE_NAME(100000, KR, Full),
+       __DEFINE_LINK_MODE_NAME(100000, SR, Full),
+       __DEFINE_LINK_MODE_NAME(100000, LR_ER_FR, Full),
+       __DEFINE_LINK_MODE_NAME(100000, DR, Full),
+       __DEFINE_LINK_MODE_NAME(100000, CR, Full),
+       __DEFINE_LINK_MODE_NAME(200000, KR2, Full),
+       __DEFINE_LINK_MODE_NAME(200000, SR2, Full),
+       __DEFINE_LINK_MODE_NAME(200000, LR2_ER2_FR2, Full),
+       __DEFINE_LINK_MODE_NAME(200000, DR2, Full),
+       __DEFINE_LINK_MODE_NAME(200000, CR2, Full),
+       __DEFINE_LINK_MODE_NAME(400000, KR4, Full),
+       __DEFINE_LINK_MODE_NAME(400000, SR4, Full),
+       __DEFINE_LINK_MODE_NAME(400000, LR4_ER4_FR4, Full),
+       __DEFINE_LINK_MODE_NAME(400000, DR4, Full),
+       __DEFINE_LINK_MODE_NAME(400000, CR4, Full),
 };
 static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
 
index fd4f3e58c6f62ca536af4f9247a5363fa81686d8..317a93129551e9c9b209f77adecd83b7bf136b5c 100644 (file)
@@ -257,6 +257,21 @@ static const struct link_mode_info link_mode_params[] = {
        __DEFINE_LINK_MODE_PARAMS(400000, DR8, Full),
        __DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
        __DEFINE_SPECIAL_MODE_PARAMS(FEC_LLRS),
+       __DEFINE_LINK_MODE_PARAMS(100000, KR, Full),
+       __DEFINE_LINK_MODE_PARAMS(100000, SR, Full),
+       __DEFINE_LINK_MODE_PARAMS(100000, LR_ER_FR, Full),
+       __DEFINE_LINK_MODE_PARAMS(100000, DR, Full),
+       __DEFINE_LINK_MODE_PARAMS(100000, CR, Full),
+       __DEFINE_LINK_MODE_PARAMS(200000, KR2, Full),
+       __DEFINE_LINK_MODE_PARAMS(200000, SR2, Full),
+       __DEFINE_LINK_MODE_PARAMS(200000, LR2_ER2_FR2, Full),
+       __DEFINE_LINK_MODE_PARAMS(200000, DR2, Full),
+       __DEFINE_LINK_MODE_PARAMS(200000, CR2, Full),
+       __DEFINE_LINK_MODE_PARAMS(400000, KR4, Full),
+       __DEFINE_LINK_MODE_PARAMS(400000, SR4, Full),
+       __DEFINE_LINK_MODE_PARAMS(400000, LR4_ER4_FR4, Full),
+       __DEFINE_LINK_MODE_PARAMS(400000, DR4, Full),
+       __DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
 };
 
 static const struct nla_policy