drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 5430ced02bac43511506e09fd3b1b5ffbe5ffa2f..193f31b8ac4a797f9552883e7d7301a52b0e72de 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1490,13 +1490,21 @@ static void dml_rq_dlg_get_dlg_params(
        disp_dlg_regs->refcyc_per_pte_group_vblank_l =
                        (unsigned int) (dst_y_per_row_vblank * (double) htotal
                                        * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
-       ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
+       if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&
+                       disp_dlg_regs->refcyc_per_pte_group_vblank_l >= (unsigned int)dml_pow(2, 13))
+               disp_dlg_regs->refcyc_per_pte_group_vblank_l = (1 << 13) - 1;
+       else
+               ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
 
        if (dual_plane) {
                disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
                                * (double) htotal * ref_freq_to_pix_freq
                                / (double) dpte_groups_per_row_ub_c);
-               ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
+               if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&
+                               disp_dlg_regs->refcyc_per_pte_group_vblank_c >= (unsigned int)dml_pow(2, 13))
+                       disp_dlg_regs->refcyc_per_pte_group_vblank_c = (1 << 13) - 1;
+               else
+                       ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
                                < (unsigned int)dml_pow(2, 13));
        }