.get_link               = ethtool_op_get_link,
 };
 
-static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
+static int nixge_mdio_read_c22(struct mii_bus *bus, int phy_id, int reg)
 {
        struct nixge_priv *priv = bus->priv;
        u32 status, tmp;
        int err;
        u16 device;
 
-       if (reg & MII_ADDR_C45) {
-               device = (reg >> 16) & 0x1f;
+       device = reg & 0x1f;
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
+       tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
 
-               tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
-                       | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
+       err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
+                                     !status, 10, 1000);
+       if (err) {
+               dev_err(priv->dev, "timeout setting read command");
+               return err;
+       }
 
-               err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
-                                             !status, 10, 1000);
-               if (err) {
-                       dev_err(priv->dev, "timeout setting address");
-                       return err;
-               }
+       status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
 
-               tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
-                       NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
-       } else {
-               device = reg & 0x1f;
+       return status;
+}
 
-               tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
-                       NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+static int nixge_mdio_read_c45(struct mii_bus *bus, int phy_id, int device,
+                              int reg)
+{
+       struct nixge_priv *priv = bus->priv;
+       u32 status, tmp;
+       int err;
+
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
+
+       tmp = NIXGE_MDIO_CLAUSE45 |
+             NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
+
+       err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
+                                     !status, 10, 1000);
+       if (err) {
+               dev_err(priv->dev, "timeout setting address");
+               return err;
        }
 
+       tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+
        nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
        nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
 
        return status;
 }
 
-static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
+static int nixge_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg,
+                               u16 val)
 {
        struct nixge_priv *priv = bus->priv;
        u32 status, tmp;
        u16 device;
        int err;
 
-       if (reg & MII_ADDR_C45) {
-               device = (reg >> 16) & 0x1f;
+       device = reg & 0x1f;
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
+       tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
 
-               tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
-                       | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
+       err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
+                                     !status, 10, 1000);
+       if (err)
+               dev_err(priv->dev, "timeout setting write command");
 
-               err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
-                                             !status, 10, 1000);
-               if (err) {
-                       dev_err(priv->dev, "timeout setting address");
-                       return err;
-               }
+       return err;
+}
 
-               tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE)
-                       | NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+static int nixge_mdio_write_c45(struct mii_bus *bus, int phy_id,
+                               int device, int reg, u16 val)
+{
+       struct nixge_priv *priv = bus->priv;
+       u32 status, tmp;
+       int err;
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
-               err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
-                                             !status, 10, 1000);
-               if (err)
-                       dev_err(priv->dev, "timeout setting write command");
-       } else {
-               device = reg & 0x1f;
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
 
-               tmp = NIXGE_MDIO_CLAUSE22 |
-                       NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
-                       NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+       tmp = NIXGE_MDIO_CLAUSE45 |
+             NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
 
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
-               nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
 
-               err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
-                                             !status, 10, 1000);
-               if (err)
-                       dev_err(priv->dev, "timeout setting write command");
+       err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
+                                     !status, 10, 1000);
+       if (err) {
+               dev_err(priv->dev, "timeout setting address");
+               return err;
        }
 
+       tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) |
+             NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
+
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
+       nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
+
+       err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
+                                     !status, 10, 1000);
+       if (err)
+               dev_err(priv->dev, "timeout setting write command");
+
        return err;
 }
 
        snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
        bus->priv = priv;
        bus->name = "nixge_mii_bus";
-       bus->read = nixge_mdio_read;
-       bus->write = nixge_mdio_write;
+       bus->read = nixge_mdio_read_c22;
+       bus->write = nixge_mdio_write_c22;
+       bus->read_c45 = nixge_mdio_read_c45;
+       bus->write_c45 = nixge_mdio_write_c45;
        bus->parent = priv->dev;
 
        priv->mii_bus = bus;