]> www.infradead.org Git - nvme.git/commitdiff
drm/amd/amdgpu: Disable MMHUB prefetch for ISP v4.1.1
authorPratap Nirujogi <pratap.nirujogi@amd.com>
Thu, 16 May 2024 06:39:14 +0000 (02:39 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Jun 2024 21:34:40 +0000 (17:34 -0400)
Disable MMHUB prefetch for ISP v4.1.1 as a temporary WA until
the GART supports MMHUB TLSi and SAW for ISP HW to access
GART memory using the TLSi path.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h

index 4e17fa03f7b5f23b5ae134ddd486a4a88eacd5fc..67f95f05ecca2e447da8b33e20a5206b04c8c1d1 100644 (file)
@@ -104,6 +104,18 @@ static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
                goto failure;
        }
 
+       /*
+        * Temporary WA added to disable MMHUB TLSi until the GART initialization
+        * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
+        * using the TLSi path
+        */
+       WREG32(mmDAGB1_WRCLI5_V4_1_1 >> 2, 0xFE5FEAA8);
+       WREG32(mmDAGB1_WRCLI9_V4_1_1 >> 2, 0xFE5FEAA8);
+       WREG32(mmDAGB1_WRCLI10_V4_1_1 >> 2, 0xFE5FEAA8);
+       WREG32(mmDAGB1_WRCLI14_V4_1_1 >> 2, 0xFE5FEAA8);
+       WREG32(mmDAGB1_WRCLI19_V4_1_1 >> 2, 0xFE5FEAA8);
+       WREG32(mmDAGB1_WRCLI20_V4_1_1 >> 2, 0xFE5FEAA8);
+
        return 0;
 
 failure:
index dfb9522c9d6a2a2b1b08a3ec37c0772528aa7125..6bfb1de191a028c8348997b05f42ae0b482fef95 100644 (file)
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
+#define mmDAGB1_WRCLI5_V4_1_1   0x68420
+#define mmDAGB1_WRCLI9_V4_1_1   0x68430
+#define mmDAGB1_WRCLI10_V4_1_1  0x68434
+#define mmDAGB1_WRCLI14_V4_1_1  0x68444
+#define mmDAGB1_WRCLI19_V4_1_1  0x68458
+#define mmDAGB1_WRCLI20_V4_1_1  0x6845C
+
 #define MAX_ISP411_INT_SRC 8
 
 void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp);