arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs

Add nodes for the multimedia IOMMU and its LARBs: this includes all but
the MJC LARB, which cannot currently be used and will be added later.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230412112739.160376-19-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 32858bf4645c834c2d77d39ce2ffb95a78235d8a..e4389bdd9c9a4a5e3fff96092bea3e9f1b1eff11 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
+#include <dt-bindings/memory/mt6795-larb-port.h>
 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
 #include <dt-bindings/power/mt6795-power.h>
 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
@@ -390,6 +391,17 @@
                        clock-names = "clk13m";
                };
 
+               iommu: iommu@10205000 {
+                       compatible = "mediatek,mt6795-m4u";
+                       reg = <0 0x10205000 0 0x1000>;
+                       clocks = <&infracfg CLK_INFRA_M4U>;
+                       clock-names = "bclk";
+                       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
+                       mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
+                       power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+                       #iommu-cells = <1>;
+               };
+
                apmixedsys: syscon@10209000 {
                        compatible = "mediatek,mt6795-apmixedsys", "syscon";
                        reg = <0 0x10209000 0 0x1000>;
@@ -667,16 +679,64 @@
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
                };
 
+               larb0: larb@14021000 {
+                       compatible = "mediatek,mt6795-smi-larb";
+                       reg = <0 0x14021000 0 0x1000>;
+                       clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
+                       clock-names = "apb", "smi";
+                       mediatek,smi = <&smi_common>;
+                       mediatek,larb-id = <0>;
+                       power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+               };
+
+               smi_common: smi@14022000 {
+                       compatible = "mediatek,mt6795-smi-common";
+                       reg = <0 0x14022000 0 0x1000>;
+                       power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+                       clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
+                       clock-names = "apb", "smi";
+               };
+
+               larb2: larb@15001000 {
+                       compatible = "mediatek,mt6795-smi-larb";
+                       reg = <0 0x15001000 0 0x1000>;
+                       clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
+                       clock-names = "apb", "smi";
+                       mediatek,smi = <&smi_common>;
+                       mediatek,larb-id = <2>;
+                       power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
+               };
+
                vdecsys: clock-controller@16000000 {
                        compatible = "mediatek,mt6795-vdecsys";
                        reg = <0 0x16000000 0 0x1000>;
                        #clock-cells = <1>;
                };
 
+               larb1: larb@16010000 {
+                       compatible = "mediatek,mt6795-smi-larb";
+                       reg = <0 0x16010000 0 0x1000>;
+                       mediatek,smi = <&smi_common>;
+                       mediatek,larb-id = <1>;
+                       clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
+               };
+
                vencsys: clock-controller@18000000 {
                        compatible = "mediatek,mt6795-vencsys";
                        reg = <0 0x18000000 0 0x1000>;
                        #clock-cells = <1>;
                };
+
+               larb3: larb@18001000 {
+                       compatible = "mediatek,mt6795-smi-larb";
+                       reg = <0 0x18001000 0 0x1000>;
+                       clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>;
+                       clock-names = "apb", "smi";
+                       mediatek,smi = <&smi_common>;
+                       mediatek,larb-id = <3>;
+                       power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;
+               };
        };
 };