return 0;
 }
 
+static int i915_reset_info(struct seq_file *m, void *unused)
+{
+       struct drm_i915_private *dev_priv = node_to_i915(m->private);
+       struct i915_gpu_error *error = &dev_priv->gpu_error;
+       struct intel_engine_cs *engine;
+       enum intel_engine_id id;
+
+       seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+
+       for_each_engine(engine, dev_priv, id) {
+               seq_printf(m, "%s = %u\n", engine->name,
+                          i915_reset_engine_count(error, engine));
+       }
+
+       return 0;
+}
+
 static int ironlake_drpc_info(struct seq_file *m)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
 static int i915_engine_info(struct seq_file *m, void *unused)
 {
        struct drm_i915_private *dev_priv = node_to_i915(m->private);
+       struct i915_gpu_error *error = &dev_priv->gpu_error;
        struct intel_engine_cs *engine;
        enum intel_engine_id id;
 
                           engine->hangcheck.seqno,
                           jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
                           engine->timeline->inflight_seqnos);
+               seq_printf(m, "\tReset count: %d\n",
+                          i915_reset_engine_count(error, engine));
 
                rcu_read_lock();
 
        {"i915_huc_load_status", i915_huc_load_status_info, 0},
        {"i915_frequency_info", i915_frequency_info, 0},
        {"i915_hangcheck_info", i915_hangcheck_info, 0},
+       {"i915_reset_info", i915_reset_info, 0},
        {"i915_drpc_info", i915_drpc_info, 0},
        {"i915_emon_status", i915_emon_status, 0},
        {"i915_ring_freq_table", i915_ring_freq_table, 0},