drm/amd/display: hook up DCN30 color blocks data to DTN log

Color caps changed between HW versions, which caused the DCN10 color
state sections in the DTN log to no longer match DCN3+ state. Create a
color state log specific to DCN3.0 and hook it up to DCN3.0+ and DCN3.1+
drivers.

rfc-v2:
- detail RAM mode for gamcor and blnd gamma blocks
- add MPC gamut remap matrix log

v3:
- read MPC gamut remap matrix in fixed 31.32 format
- extend to DCN3.0+ and DCN3.1+ drivers (Harry)

Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 1963a3dc814d630f7443e04fd581306445a65dcf..2ab5dfcc326d283f283d326f18d0fae54054bd44 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -375,7 +375,10 @@ void dcn10_log_hw_state(struct dc *dc,
 
        dcn10_log_hubp_states(dc, log_ctx);
 
-       dcn10_log_color_state(dc, log_ctx);
+       if (dc->hwss.log_color_state)
+               dc->hwss.log_color_state(dc, log_ctx);
+       else
+               dcn10_log_color_state(dc, log_ctx);
 
        DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow blank_en\n");
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index c34c13e1e0a4ea918de9a9e36dbe305ce5224485..24d4e19f90c8aca71605586fb816c895408ae9f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -69,6 +69,132 @@
 #define FN(reg_name, field_name) \
        hws->shifts->field_name, hws->masks->field_name
 
+void dcn30_log_color_state(struct dc *dc,
+                          struct dc_log_buffer_ctx *log_ctx)
+{
+       struct dc_context *dc_ctx = dc->ctx;
+       struct resource_pool *pool = dc->res_pool;
+       int i;
+
+       DTN_INFO("DPP:  DGAM ROM  DGAM ROM type  DGAM LUT  SHAPER mode"
+                "  3DLUT mode  3DLUT bit depth  3DLUT size  RGAM mode"
+                "  GAMUT adjust  "
+                "C11        C12        C13        C14        "
+                "C21        C22        C23        C24        "
+                "C31        C32        C33        C34        \n");
+
+       for (i = 0; i < pool->pipe_count; i++) {
+               struct dpp *dpp = pool->dpps[i];
+               struct dcn_dpp_state s = {0};
+
+               dpp->funcs->dpp_read_state(dpp, &s);
+               dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
+
+               if (!s.is_enabled)
+                       continue;
+
+               DTN_INFO("[%2d]:  %7x  %13s  %8s  %11s  %10s  %15s  %10s  %9s"
+                        "  %12s  "
+                        "%010lld %010lld %010lld %010lld "
+                        "%010lld %010lld %010lld %010lld "
+                        "%010lld %010lld %010lld %010lld",
+                       dpp->inst,
+                       s.pre_dgam_mode,
+                       (s.pre_dgam_select == 0) ? "sRGB" :
+                        ((s.pre_dgam_select == 1) ? "Gamma 2.2" :
+                        ((s.pre_dgam_select == 2) ? "Gamma 2.4" :
+                        ((s.pre_dgam_select == 3) ? "Gamma 2.6" :
+                        ((s.pre_dgam_select == 4) ? "BT.709" :
+                        ((s.pre_dgam_select == 5) ? "PQ" :
+                        ((s.pre_dgam_select == 6) ? "HLG" :
+                                                    "Unknown")))))),
+                       (s.gamcor_mode == 0) ? "Bypass" :
+                        ((s.gamcor_mode == 1) ? "RAM A" :
+                                                "RAM B"),
+                       (s.shaper_lut_mode == 1) ? "RAM A" :
+                        ((s.shaper_lut_mode == 2) ? "RAM B" :
+                                                    "Bypass"),
+                       (s.lut3d_mode == 1) ? "RAM A" :
+                        ((s.lut3d_mode == 2) ? "RAM B" :
+                                               "Bypass"),
+                       (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
+                       (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
+                       (s.rgam_lut_mode == 0) ? "Bypass" :
+                        ((s.rgam_lut_mode == 1) ? "RAM A" :
+                                                  "RAM B"),
+                       (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
+                               ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
+                                                                         "SW"),
+                       s.gamut_remap.temperature_matrix[0].value,
+                       s.gamut_remap.temperature_matrix[1].value,
+                       s.gamut_remap.temperature_matrix[2].value,
+                       s.gamut_remap.temperature_matrix[3].value,
+                       s.gamut_remap.temperature_matrix[4].value,
+                       s.gamut_remap.temperature_matrix[5].value,
+                       s.gamut_remap.temperature_matrix[6].value,
+                       s.gamut_remap.temperature_matrix[7].value,
+                       s.gamut_remap.temperature_matrix[8].value,
+                       s.gamut_remap.temperature_matrix[9].value,
+                       s.gamut_remap.temperature_matrix[10].value,
+                       s.gamut_remap.temperature_matrix[11].value);
+               DTN_INFO("\n");
+       }
+       DTN_INFO("\n");
+
+       DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE"
+                "  SHAPER mode  3DLUT mode  3DLUT bit-depth  3DLUT size  OGAM mode  OGAM LUT"
+                "  GAMUT adjust  "
+                "C11        C12        C13        C14        "
+                "C21        C22        C23        C24        "
+                "C31        C32        C33        C34        \n");
+
+       for (i = 0; i < pool->pipe_count; i++) {
+               struct mpcc_state s = {0};
+
+               pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
+               mpc3_get_gamut_remap(pool->mpc, i,  &s.gamut_remap);
+
+               if (s.opp_id != 0xf)
+                       DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d  %11s %11s %16s %11s %10s %9s"
+                                "  %-12s  "
+                                "%010lld %010lld %010lld %010lld "
+                                "%010lld %010lld %010lld %010lld "
+                                "%010lld %010lld %010lld %010lld\n",
+                               i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
+                               s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
+                               s.idle,
+                               (s.shaper_lut_mode == 1) ? "RAM A" :
+                                ((s.shaper_lut_mode == 2) ? "RAM B" :
+                                                            "Bypass"),
+                               (s.lut3d_mode == 1) ? "RAM A" :
+                                ((s.lut3d_mode == 2) ? "RAM B" :
+                                                       "Bypass"),
+                               (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
+                               (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
+                               (s.rgam_mode == 0) ? "Bypass" :
+                                ((s.rgam_mode == 2) ? "RAM" :
+                                                      "Unknown"),
+                               (s.rgam_mode == 1) ? "B" : "A",
+                               (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
+                                       ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
+                                                                                 "SW"),
+                               s.gamut_remap.temperature_matrix[0].value,
+                               s.gamut_remap.temperature_matrix[1].value,
+                               s.gamut_remap.temperature_matrix[2].value,
+                               s.gamut_remap.temperature_matrix[3].value,
+                               s.gamut_remap.temperature_matrix[4].value,
+                               s.gamut_remap.temperature_matrix[5].value,
+                               s.gamut_remap.temperature_matrix[6].value,
+                               s.gamut_remap.temperature_matrix[7].value,
+                               s.gamut_remap.temperature_matrix[8].value,
+                               s.gamut_remap.temperature_matrix[9].value,
+                               s.gamut_remap.temperature_matrix[10].value,
+                               s.gamut_remap.temperature_matrix[11].value);
+
+       }
+       DTN_INFO("\n");
+}
+
 bool dcn30_set_blend_lut(
        struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
index e557e2b9861870bb17ed1ac70f73e636888528d1..4248a4c0e574c441c9e78f424c61f5f7c626b0cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
@@ -52,6 +52,9 @@ bool dcn30_mmhubbub_warmup(
        unsigned int num_dwb,
        struct dc_writeback_info *wb_info);
 
+void dcn30_log_color_state(struct dc *dc,
+                          struct dc_log_buffer_ctx *log_ctx);
+
 bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
                const struct dc_plane_state *plane_state);
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index a54399383318145b8bc72fc85e646bf546588609..91b1b43a728fd681fe28d4ba8e479101298b5101 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -339,6 +339,8 @@ struct hw_sequencer_funcs {
 
        /* HW State Logging Related */
        void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
+       void (*log_color_state)(struct dc *dc,
+                               struct dc_log_buffer_ctx *log_ctx);
        void (*get_hw_state)(struct dc *dc, char *pBuf,
                        unsigned int bufSize, unsigned int mask);
        void (*clear_status_bits)(struct dc *dc, unsigned int mask);