if (((vars->line_speed == SPEED_AUTO_NEG) &&
             (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
            (vars->line_speed == SPEED_1000)) {
-               u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
+               u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
                an_adv |= (1<<5);
 
                /* Enable CL37 1G Parallel Detect */
                                            port_mb[port].link_status));
 
        /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
-       if (bp->link_params.loopback_mode != LOOPBACK_NONE &&
-           bp->link_params.loopback_mode != LOOPBACK_EXT)
+       if (params->loopback_mode != LOOPBACK_NONE &&
+           params->loopback_mode != LOOPBACK_EXT)
                vars->link_status |= LINK_STATUS_LINK_UP;
 
        if (bnx2x_eee_has_cap(params))
        } else {
                /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
                /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
-               for (i = 0; i < ARRAY_SIZE(reg_set);
-                     i++)
+               for (i = 0; i < ARRAY_SIZE(reg_set); i++)
                        bnx2x_cl45_write(bp, phy, reg_set[i].devad,
                                         reg_set[i].reg, reg_set[i].val);
 
 
                bnx2x_xgxs_deassert(params);
 
-               /* set bmac loopback */
+               /* Set bmac loopback */
                bnx2x_bmac_enable(params, vars, 1, 1);
 
                REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
                vars->phy_flags = PHY_XGXS_FLAG;
 
                bnx2x_xgxs_deassert(params);
-               /* set bmac loopback */
+               /* Set bmac loopback */
                bnx2x_emac_enable(params, vars, 1);
                bnx2x_emac_program(params, vars);
                REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
                   params->req_line_speed[0], params->req_flow_ctrl[0]);
        DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
                   params->req_line_speed[1], params->req_flow_ctrl[1]);
+       DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
        vars->link_status = 0;
        vars->phy_link_up = 0;
        vars->link_up = 0;
        }
 
        /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
-        * since some switches tend to reinit the AN process and clear the
-        * advertised BP/NP after ~2 seconds causing the KR2 to be disabled
+        * Since some switches tend to reinit the AN process and clear the
+        * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
         * and recovered many times
         */
        if (vars->check_kr2_recovery_cnt > 0) {
 
        /* CL73 has not begun yet */
        if (base_page == 0) {
-               if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
+               if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
                        bnx2x_kr2_recovery(params, vars, phy);
+                       DP(NETIF_MSG_LINK, "No BP\n");
+               }
                return;
        }
 
        if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
                if (!not_kr2_device) {
                        DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
-                                      next_page);
+                          next_page);
                        bnx2x_kr2_recovery(params, vars, phy);
                }
                return;