MIPS: barrier: Clean up __smp_mb() definition

We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.

Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org

diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index f36cab87cfdef52a1e5460feda61bccffef84e39..8a5abc1c85a6dac112309e9c6393d7e13077dfcb 100644 (file)
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -89,17 +89,13 @@ static inline void wmb(void)
 #endif /* !CONFIG_CPU_HAS_WB */
 
 #if defined(CONFIG_WEAK_ORDERING)
-# ifdef CONFIG_CPU_CAVIUM_OCTEON
-#  define __smp_mb()   __sync()
-# else
-#  define __smp_mb()   __asm__ __volatile__("sync" : : :"memory")
-# endif
+# define __smp_mb()    __sync()
 # define __smp_rmb()   rmb()
 # define __smp_wmb()   wmb()
 #else
-#define __smp_mb()     barrier()
-#define __smp_rmb()    barrier()
-#define __smp_wmb()    barrier()
+# define __smp_mb()    barrier()
+# define __smp_rmb()   barrier()
+# define __smp_wmb()   barrier()
 #endif
 
 /*