static unsigned long saved_cr4;
 static DEFINE_RAW_SPINLOCK(cache_disable_lock);
 
+/*
+ * Cache flushing is the most time-consuming step when programming the
+ * MTRRs.  On many Intel CPUs without known erratas, it can be skipped
+ * if the CPU declares cache self-snooping support.
+ */
+static void maybe_flush_caches(void)
+{
+       if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
+               wbinvd();
+}
+
 void cache_disable(void) __acquires(cache_disable_lock)
 {
        unsigned long cr0;
        cr0 = read_cr0() | X86_CR0_CD;
        write_cr0(cr0);
 
-       /*
-        * Cache flushing is the most time-consuming step when programming
-        * the MTRRs. Fortunately, as per the Intel Software Development
-        * Manual, we can skip it if the processor supports cache self-
-        * snooping.
-        */
-       if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
-               wbinvd();
+       maybe_flush_caches();
 
        /* Save value of CR4 and clear Page Global Enable (bit 7) */
        if (cpu_feature_enabled(X86_FEATURE_PGE)) {
        if (cpu_feature_enabled(X86_FEATURE_MTRR))
                mtrr_disable();
 
-       /* Again, only flush caches if we have to. */
-       if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
-               wbinvd();
+       maybe_flush_caches();
 }
 
 void cache_enable(void) __releases(cache_disable_lock)