arm64: dts: ti: k3-j722s-main: Add R5F and C7x remote processor nodes

The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each
of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems
in MAIN voltage domain. Add the DT nodes to support Inter-Processor
Communication.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
[ refactoring changes to k3-j722s-main.dtsi ]
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240830161742.925145-2-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index cadb4f7c2ea941b59ac75acfb8e130ac42e0073e..ed6f4ba08afca157561fa2310e31b81f1e429720 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -153,6 +153,67 @@
                        dr_mode = "otg";
                };
        };
+
+       main_r5fss0: r5fss@78400000 {
+               compatible = "ti,am62-r5fss";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x78400000 0x00 0x78400000 0x8000>,
+                        <0x78500000 0x00 0x78500000 0x8000>;
+               power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
+
+               main_r5fss0_core0: r5f@78400000 {
+                       compatible = "ti,am62-r5f";
+                       reg = <0x78400000 0x00008000>,
+                             <0x78500000 0x00008000>;
+                       reg-names = "atcm", "btcm";
+                       resets = <&k3_reset 262 1>;
+                       firmware-name = "j722s-main-r5f0_0-fw";
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <262>;
+                       ti,sci-proc-ids = <0x04 0xff>;
+                       ti,atcm-enable = <1>;
+                       ti,btcm-enable = <1>;
+                       ti,loczrama = <1>;
+               };
+       };
+
+       c7x_0: dsp@7e000000 {
+               compatible = "ti,am62a-c7xv-dsp";
+               reg = <0x00 0x7e000000 0x00 0x00200000>;
+               reg-names = "l2sram";
+               resets = <&k3_reset 208 1>;
+               firmware-name = "j722s-c71_0-fw";
+               ti,sci = <&dmsc>;
+               ti,sci-dev-id = <208>;
+               ti,sci-proc-ids = <0x30 0xff>;
+               status = "disabled";
+       };
+
+       c7x_1: dsp@7e200000 {
+               compatible = "ti,am62a-c7xv-dsp";
+               reg = <0x00 0x7e200000 0x00 0x00200000>;
+               reg-names = "l2sram";
+               resets = <&k3_reset 268 1>;
+               firmware-name = "j722s-c71_1-fw";
+               ti,sci = <&dmsc>;
+               ti,sci-dev-id = <268>;
+               ti,sci-proc-ids = <0x31 0xff>;
+               status = "disabled";
+       };
+};
+
+/* MCU domain overrides */
+
+&mcu_r5fss0_core0 {
+       firmware-name = "j722s-mcu-r5f0_0-fw";
+};
+
+/* Wakeup domain overrides */
+
+&wkup_r5fss0_core0 {
+       firmware-name = "j722s-wkup-r5f0_0-fw";
 };
 
 &main_conf {