drm/msm/dpu: sm8550: remove unused VIG and DMA clock controls entries

The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the
duplicate clock controls from the MDP top.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562330/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 32d569bf9c20ca638d802d21e489ec443e450e2a..08d12327cbdbb4b4a7e932bc32add83c9ce31c7d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -24,16 +24,6 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
        .base = 0, .len = 0x494,
        .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
        .clk_ctrls = {
-               [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
-               [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
-               [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
-               [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
-               [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
                [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
        },
 };
@@ -81,7 +71,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_vig_sblk_0,
                .xin_id = 0,
                .type = SSPP_TYPE_VIG,
-               .clk_ctrl = DPU_CLK_CTRL_VIG0,
        }, {
                .name = "sspp_1", .id = SSPP_VIG1,
                .base = 0x6000, .len = 0x344,
@@ -89,7 +78,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_vig_sblk_1,
                .xin_id = 4,
                .type = SSPP_TYPE_VIG,
-               .clk_ctrl = DPU_CLK_CTRL_VIG1,
        }, {
                .name = "sspp_2", .id = SSPP_VIG2,
                .base = 0x8000, .len = 0x344,
@@ -97,7 +85,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_vig_sblk_2,
                .xin_id = 8,
                .type = SSPP_TYPE_VIG,
-               .clk_ctrl = DPU_CLK_CTRL_VIG2,
        }, {
                .name = "sspp_3", .id = SSPP_VIG3,
                .base = 0xa000, .len = 0x344,
@@ -105,7 +92,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_vig_sblk_3,
                .xin_id = 12,
                .type = SSPP_TYPE_VIG,
-               .clk_ctrl = DPU_CLK_CTRL_VIG3,
        }, {
                .name = "sspp_8", .id = SSPP_DMA0,
                .base = 0x24000, .len = 0x344,
@@ -113,7 +99,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sdm845_dma_sblk_0,
                .xin_id = 1,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA0,
        }, {
                .name = "sspp_9", .id = SSPP_DMA1,
                .base = 0x26000, .len = 0x344,
@@ -121,7 +106,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sdm845_dma_sblk_1,
                .xin_id = 5,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA1,
        }, {
                .name = "sspp_10", .id = SSPP_DMA2,
                .base = 0x28000, .len = 0x344,
@@ -129,7 +113,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sdm845_dma_sblk_2,
                .xin_id = 9,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA2,
        }, {
                .name = "sspp_11", .id = SSPP_DMA3,
                .base = 0x2a000, .len = 0x344,
@@ -137,7 +120,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sdm845_dma_sblk_3,
                .xin_id = 13,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA3,
        }, {
                .name = "sspp_12", .id = SSPP_DMA4,
                .base = 0x2c000, .len = 0x344,
@@ -145,7 +127,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_dma_sblk_4,
                .xin_id = 14,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA4,
        }, {
                .name = "sspp_13", .id = SSPP_DMA5,
                .base = 0x2e000, .len = 0x344,
@@ -153,7 +134,6 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
                .sblk = &sm8550_dma_sblk_5,
                .xin_id = 15,
                .type = SSPP_TYPE_DMA,
-               .clk_ctrl = DPU_CLK_CTRL_DMA5,
        },
 };