clk: renesas: r9a09g047: Add DMAC clocks and resets

Add clock and reset entries for the Renesas RZ/G3E DMAC IPs.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250801084825.471011-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 26e2be7667eb47e2ac5c6dd2c9b4a9edcf284d48..4e8881e0006b4b91adde375164c1eeb88eabcff5 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -48,6 +48,8 @@ enum clk_ids {
        CLK_PLLDTY_ACPU_DIV2,
        CLK_PLLDTY_ACPU_DIV4,
        CLK_PLLDTY_DIV8,
+       CLK_PLLDTY_RCPU,
+       CLK_PLLDTY_RCPU_DIV4,
        CLK_PLLETH_DIV_250_FIX,
        CLK_PLLETH_DIV_125_FIX,
        CLK_CSDIV_PLLETH_GBE0,
@@ -157,6 +159,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
        DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
        DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
+       DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
+       DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
 
        DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
        DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
@@ -180,6 +184,16 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 };
 
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
+       DEF_MOD("dmac_0_aclk",                  CLK_PLLCM33_GEAR, 0, 0, 0, 0,
+                                               BUS_MSTOP(5, BIT(9))),
+       DEF_MOD("dmac_1_aclk",                  CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
+                                               BUS_MSTOP(3, BIT(2))),
+       DEF_MOD("dmac_2_aclk",                  CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
+                                               BUS_MSTOP(3, BIT(3))),
+       DEF_MOD("dmac_3_aclk",                  CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
+                                               BUS_MSTOP(10, BIT(11))),
+       DEF_MOD("dmac_4_aclk",                  CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
+                                               BUS_MSTOP(10, BIT(12))),
        DEF_MOD_CRITICAL("icu_0_pclk_i",        CLK_PLLCM33_DIV16, 0, 5, 0, 5,
                                                BUS_MSTOP_NONE),
        DEF_MOD_CRITICAL("gic_0_gicclk",        CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
@@ -300,6 +314,11 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
+       DEF_RST(3, 1, 1, 2),            /* DMAC_0_ARESETN */
+       DEF_RST(3, 2, 1, 3),            /* DMAC_1_ARESETN */
+       DEF_RST(3, 3, 1, 4),            /* DMAC_2_ARESETN */
+       DEF_RST(3, 4, 1, 5),            /* DMAC_3_ARESETN */
+       DEF_RST(3, 5, 1, 6),            /* DMAC_4_ARESETN */
        DEF_RST(3, 6, 1, 7),            /* ICU_0_PRESETN_I */
        DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
        DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */