]> www.infradead.org Git - users/willy/linux.git/commitdiff
arm64: zynqmp: Add missing description for efuses
authorMichal Simek <michal.simek@amd.com>
Mon, 27 May 2024 09:34:09 +0000 (11:34 +0200)
committerMichal Simek <michal.simek@amd.com>
Mon, 17 Jun 2024 06:36:21 +0000 (08:36 +0200)
The commit 737c0c8d07b5 ("nvmem: zynqmp_nvmem: Add support to access
efuse") added support for efuses that's why also describe them in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/beb8002f8dae47ce6f38f7f961d024e65372b654.1716802450.git.michal.simek@amd.com
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index a43c646254020a24b5e626458ad5e3045edb8503..635b67c06c4efb4e3c304e1a0ba61a965f6fcd13 100644 (file)
                                        soc_revision: soc-revision@0 {
                                                reg = <0x0 0x4>;
                                        };
+                                       /* efuse access */
+                                       efuse_dna: efuse-dna@c {
+                                               reg = <0xc 0xc>;
+                                       };
+                                       efuse_usr0: efuse-usr0@20 {
+                                               reg = <0x20 0x4>;
+                                       };
+                                       efuse_usr1: efuse-usr1@24 {
+                                               reg = <0x24 0x4>;
+                                       };
+                                       efuse_usr2: efuse-usr2@28 {
+                                               reg = <0x28 0x4>;
+                                       };
+                                       efuse_usr3: efuse-usr3@2c {
+                                               reg = <0x2c 0x4>;
+                                       };
+                                       efuse_usr4: efuse-usr4@30 {
+                                               reg = <0x30 0x4>;
+                                       };
+                                       efuse_usr5: efuse-usr5@34 {
+                                               reg = <0x34 0x4>;
+                                       };
+                                       efuse_usr6: efuse-usr6@38 {
+                                               reg = <0x38 0x4>;
+                                       };
+                                       efuse_usr7: efuse-usr7@3c {
+                                               reg = <0x3c 0x4>;
+                                       };
+                                       efuse_miscusr: efuse-miscusr@40 {
+                                               reg = <0x40 0x4>;
+                                       };
+                                       efuse_chash: efuse-chash@50 {
+                                               reg = <0x50 0x4>;
+                                       };
+                                       efuse_pufmisc: efuse-pufmisc@54 {
+                                               reg = <0x54 0x4>;
+                                       };
+                                       efuse_sec: efuse-sec@58 {
+                                               reg = <0x58 0x4>;
+                                       };
+                                       efuse_spkid: efuse-spkid@5c {
+                                               reg = <0x5c 0x4>;
+                                       };
+                                       efuse_aeskey: efuse-aeskey@60 {
+                                               reg = <0x60 0x20>;
+                                       };
+                                       efuse_ppk0hash: efuse-ppk0hash@a0 {
+                                               reg = <0xa0 0x30>;
+                                       };
+                                       efuse_ppk1hash: efuse-ppk1hash@d0 {
+                                               reg = <0xd0 0x30>;
+                                       };
+                                       efuse_pufuser: efuse-pufuser@100 {
+                                               reg = <0x100 0x7F>;
+                                       };
                                };
                        };