Instead of software managed counters.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 #define MCA_REG__STATUS__ERRORCODEEXT(x)       MCA_REG_FIELD(x, 21, 16)
 #define MCA_REG__STATUS__ERRORCODE(x)          MCA_REG_FIELD(x, 15, 0)
 
+#define MCA_REG__MISC0__ERRCNT(x)              MCA_REG_FIELD(x, 43, 32)
+
 #define MCA_REG__SYND__ERRORINFORMATION(x)     MCA_REG_FIELD(x, 17, 0)
 
 enum amdgpu_mca_ip {
 
                                          uint32_t *count)
 {
        u32 ext_error_code;
+       u32 err_cnt;
 
        ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
+       err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
 
        if (type == AMDGPU_MCA_ERROR_TYPE_UE && ext_error_code == 0)
-               *count = 1;
+               *count = err_cnt;
        else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
-               *count = 1;
+               *count = err_cnt;
 
        return 0;
 }