arm64: dts: renesas: r9a08g045: Add DMAC node

Add DMAC node.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0d5c47a65e46c584f79a1ec3a3dac011413520a7..37885cd24f168e5cf83e737530e4be7246aa5b45 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -181,6 +181,44 @@
                        resets = <&cpg R9A08G045_IA55_RESETN>;
                };
 
+               dmac: dma-controller@11820000 {
+                       compatible = "renesas,r9a08g045-dmac",
+                                    "renesas,rz-dmac";
+                       reg = <0 0x11820000 0 0x10000>,
+                             <0 0x11830000 0 0x10000>;
+                       interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
+                                <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
+                       clock-names = "main", "register";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G045_DMAC_ARESETN>,
+                                <&cpg R9A08G045_DMAC_RST_ASYNC>;
+                       reset-names = "arst", "rst_async";
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+               };
+
                sdhi0: mmc@11c00000  {
                        compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
                        reg = <0x0 0x11c00000 0 0x10000>;