drm/i915: Simplify PIPESRC_ERLY_TPT definition

PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index b44809899502b934cdde2d00cc6d0c2b79d08e10..7983cbaf83f7d67697573733751999f4c9981987 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane,
 
        intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
 
-       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
+       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
                       PIPESRC_HEIGHT(et_y_position));
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d18baeb971bbe7d19dff0733a142147defd24dbc..f59238d3d48405fc4100588929fe820d680e9767 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2384,7 +2384,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
        if (!crtc_state->enable_psr2_su_region_et)
                return;
 
-       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
+       intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
                       crtc_state->pipe_srcsz_early_tpt);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index b6a39926ccb6ee0bf5d84c6044986cadec272134..23851513054a5a74ef689ba51b231a336aa0e141 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -252,8 +252,8 @@
 
 /* PSR2 Early transport */
 #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
-
-#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)   _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
+#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
+#define PIPE_SRCSZ_ERLY_TPT(pipe)      _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
 
 #define _SEL_FETCH_PLANE_BASE_1_A              0x70890
 #define _SEL_FETCH_PLANE_BASE_2_A              0x708B0