drm/etnaviv: enable debug registers on demand

Some performance register are debug register and they need to
be enabled in order to be functional.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index c00086d755809cbb4318ad680269e858907f7f90..51b3fbea1bf0dd7b83a7644ea4f802d77f5d554e 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -1353,6 +1353,11 @@ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
        val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
        gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
 
+       /* enable debug register */
+       val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+       val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+       gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+
        sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
 }
 
@@ -1371,6 +1376,11 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
                *pmr->bo_vma = pmr->sequence;
        }
 
+       /* disable debug register */
+       val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+       val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
+       gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
+
        /* enable clock gating */
        val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
        val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;