#include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
+#include "exynos_drm_fb.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_iommu.h"
 
 {
        struct decon_context *ctx = crtc->ctx;
        struct drm_plane_state *state = plane->base.state;
+       struct drm_framebuffer *fb = state->fb;
        unsigned int win = plane->zpos;
-       unsigned int bpp = state->fb->bits_per_pixel >> 3;
-       unsigned int pitch = state->fb->pitches[0];
+       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int pitch = fb->pitches[0];
+       dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
        u32 val;
 
        if (test_bit(BIT_SUSPENDED, &ctx->flags))
                VIDOSD_Wx_ALPHA_B_F(0x0);
        writel(val, ctx->addr + DECON_VIDOSDxD(win));
 
-       writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win));
+       writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 
-       val = plane->dma_addr[0] + pitch * plane->crtc_h;
+       val = dma_addr + pitch * plane->crtc_h;
        writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 
        if (ctx->out_type != IFTYPE_HDMI)
                        | BIT_VAL(plane->crtc_w * bpp, 14, 0);
        writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 
-       decon_win_set_pixfmt(ctx, win, state->fb);
+       decon_win_set_pixfmt(ctx, win, fb);
 
        /* window enable */
        decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_drv.h"
+#include "exynos_drm_fb.h"
 #include "exynos_drm_fbdev.h"
 #include "exynos_drm_iommu.h"
 
 {
        struct decon_context *ctx = crtc->ctx;
        struct drm_plane_state *state = plane->base.state;
+       struct drm_framebuffer *fb = state->fb;
        int padding;
        unsigned long val, alpha;
        unsigned int last_x;
        unsigned int last_y;
        unsigned int win = plane->zpos;
-       unsigned int bpp = state->fb->bits_per_pixel >> 3;
-       unsigned int pitch = state->fb->pitches[0];
+       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int pitch = fb->pitches[0];
 
        if (ctx->suspended)
                return;
         */
 
        /* buffer start address */
-       val = (unsigned long)plane->dma_addr[0];
+       val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
        writel(val, ctx->regs + VIDW_BUF_START(win));
 
-       padding = (pitch / bpp) - state->fb->width;
+       padding = (pitch / bpp) - fb->width;
 
        /* buffer size */
-       writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
-       writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win));
+       writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
+       writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
 
        /* offset from the start of the buffer to read */
        writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win));
 
        writel(alpha, ctx->regs + VIDOSD_D(win));
 
-       decon_win_set_pixfmt(ctx, win, state->fb);
+       decon_win_set_pixfmt(ctx, win, fb);
 
        /* hardware window 0 doesn't support color key. */
        if (win != 0)
 
  * @crtc_h: window height to be displayed (hardware screen).
  * @h_ratio: horizontal scaling ratio, 16.16 fixed point
  * @v_ratio: vertical scaling ratio, 16.16 fixed point
- * @dma_addr: array of bus(accessed by dma) address to the memory region
- *           allocated for a overlay.
  * @zpos: order of overlay layer(z position).
  *
  * this structure is common to exynos SoC and its contents would be copied
        unsigned int crtc_h;
        unsigned int h_ratio;
        unsigned int v_ratio;
-       dma_addr_t dma_addr[MAX_FB_BUFFER];
        unsigned int zpos;
        struct drm_framebuffer *pending_fb;
 };
 
 struct exynos_drm_fb {
        struct drm_framebuffer  fb;
        struct exynos_drm_gem   *exynos_gem[MAX_FB_BUFFER];
+       dma_addr_t                      dma_addr[MAX_FB_BUFFER];
 };
 
 static int check_fb_gem_memory_type(struct drm_device *drm_dev,
                        goto err;
 
                exynos_fb->exynos_gem[i] = exynos_gem[i];
+               exynos_fb->dma_addr[i] = exynos_gem[i]->dma_addr
+                                               + mode_cmd->offsets[i];
        }
 
        drm_helper_mode_fill_fb_struct(&exynos_fb->fb, mode_cmd);
        return ERR_PTR(ret);
 }
 
-struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index)
+dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index)
 {
        struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb);
-       struct exynos_drm_gem *exynos_gem;
 
        if (index >= MAX_FB_BUFFER)
-               return NULL;
+               return DMA_ERROR_CODE;
 
-       exynos_gem = exynos_fb->exynos_gem[index];
-       if (!exynos_gem)
-               return NULL;
-
-       DRM_DEBUG_KMS("dma_addr: 0x%lx\n", (unsigned long)exynos_gem->dma_addr);
-
-       return exynos_gem;
+       return exynos_fb->dma_addr[index];
 }
 
 static void exynos_drm_output_poll_changed(struct drm_device *dev)
 
                            struct exynos_drm_gem **exynos_gem,
                            int count);
 
-/* get gem object of a drm framebuffer */
-struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index);
+dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index);
 
 void exynos_drm_mode_config_init(struct drm_device *dev);
 
 
 #include <drm/exynos_drm.h>
 
 #include "exynos_drm_drv.h"
+#include "exynos_drm_fb.h"
 #include "exynos_drm_fbdev.h"
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_plane.h"
 {
        struct fimd_context *ctx = crtc->ctx;
        struct drm_plane_state *state = plane->base.state;
+       struct drm_framebuffer *fb = state->fb;
        dma_addr_t dma_addr;
        unsigned long val, size, offset;
        unsigned int last_x, last_y, buf_offsize, line_size;
        unsigned int win = plane->zpos;
-       unsigned int bpp = state->fb->bits_per_pixel >> 3;
-       unsigned int pitch = state->fb->pitches[0];
+       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int pitch = fb->pitches[0];
 
        if (ctx->suspended)
                return;
        offset += plane->src_y * pitch;
 
        /* buffer start address */
-       dma_addr = plane->dma_addr[0] + offset;
+       dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
        val = (unsigned long)dma_addr;
        writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 
                DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
        }
 
-       fimd_win_set_pixfmt(ctx, win, state->fb);
+       fimd_win_set_pixfmt(ctx, win, fb);
 
        /* hardware window 0 doesn't support color key. */
        if (win != 0)
 
                                     struct drm_plane_state *state)
 {
        struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane);
-       int nr;
-       int i;
 
        if (!state->fb)
                return 0;
 
-       nr = drm_format_num_planes(state->fb->pixel_format);
-       for (i = 0; i < nr; i++) {
-               struct exynos_drm_gem *exynos_gem =
-                                       exynos_drm_fb_gem(state->fb, i);
-               if (!exynos_gem) {
-                       DRM_DEBUG_KMS("gem object is null\n");
-                       return -EFAULT;
-               }
-
-               exynos_plane->dma_addr[i] = exynos_gem->dma_addr +
-                                           state->fb->offsets[i];
-
-               DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n",
-                               i, (unsigned long)exynos_plane->dma_addr[i]);
-       }
-
        return 0;
 }
 
 
 
 #include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
+#include "exynos_drm_fb.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_vidi.h"
 
 static void vidi_update_plane(struct exynos_drm_crtc *crtc,
                              struct exynos_drm_plane *plane)
 {
+       struct drm_plane_state *state = plane->base.state;
        struct vidi_context *ctx = crtc->ctx;
+       dma_addr_t addr;
 
        if (ctx->suspended)
                return;
 
-       DRM_DEBUG_KMS("dma_addr = %pad\n", plane->dma_addr);
+       addr = exynos_drm_fb_dma_addr(state->fb, 0);
+       DRM_DEBUG_KMS("dma_addr = %pad\n", &addr);
 
        if (ctx->vblank_on)
                schedule_work(&ctx->work);
 
 
 #include "exynos_drm_drv.h"
 #include "exynos_drm_crtc.h"
+#include "exynos_drm_fb.h"
 #include "exynos_drm_plane.h"
 #include "exynos_drm_iommu.h"
 
                return;
        }
 
-       luma_addr[0] = plane->dma_addr[0];
-       chroma_addr[0] = plane->dma_addr[1];
+       luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
+       chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
 
        if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
                ctx->interlace = true;
        dst_y_offset = plane->crtc_y;
 
        /* converting dma address base and source offset */
-       dma_addr = plane->dma_addr[0]
+       dma_addr = exynos_drm_fb_dma_addr(fb, 0)
                + (plane->src_x * fb->bits_per_pixel >> 3)
                + (plane->src_y * fb->pitches[0]);
        src_x_offset = 0;