bool "Insn: div, divu, rem, remu"
        default y
 
-config ARC_HAS_RTC
-       bool "Local 64-bit r/o cycle counter"
-       default n
-       depends on !SMP
-
-config ARC_HAS_GFRC
-       bool "SMP synchronized 64-bit cycle counter"
+config ARC_TIMERS_64BIT
+       bool "64-bit r/o cycle counters RTC (up) and GFRC (smp)"
        default y
-       depends on SMP
 
 config ARC_NUMBER_OF_INTERRUPTS
        int "Number of interrupts"
 
                       is_isa_arcompact() ? "ARCompact" : "ARCv2",
                       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
 
-       n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
+       n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
                       IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
                       IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
-                      IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
-                                CONFIG_ARC_HAS_RTC));
+                      IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
+                      IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
 
        n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
                           IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 
 
 /********** Clock Source Device *********/
 
-#ifdef CONFIG_ARC_HAS_GFRC
+#ifdef CONFIG_ARC_TIMERS_64BIT
 
 static cycle_t arc_read_gfrc(struct clocksource *cs)
 {
 }
 CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
 
-#endif
-
-#ifdef CONFIG_ARC_HAS_RTC
-
 #define AUX_RTC_CTRL   0x103
 #define AUX_RTC_LOW    0x104
 #define AUX_RTC_HIGH   0x105