ocram-ecc@ff8c3000 {
                                compatible = "altr,socfpga-a10-ocram-ecc";
                                reg = <0xff8c3000 0x400>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+                                            <33 IRQ_TYPE_LEVEL_HIGH>;
                        };
 +
 +                      emac0-rx-ecc@ff8c0800 {
 +                              compatible = "altr,socfpga-eth-mac-ecc";
 +                              reg = <0xff8c0800 0x400>;
 +                              altr,ecc-parent = <&gmac0>;
 +                              interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <36 IRQ_TYPE_LEVEL_HIGH>;
 +                      };
 +
 +                      emac0-tx-ecc@ff8c0c00 {
 +                              compatible = "altr,socfpga-eth-mac-ecc";
 +                              reg = <0xff8c0c00 0x400>;
 +                              altr,ecc-parent = <&gmac0>;
 +                              interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <37 IRQ_TYPE_LEVEL_HIGH>;
 +                      };
                };
  
                rst: rstmgr@ffd05000 {
 
                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                        };
+ 
+                       uart0_pins_a: uart0@0 {
+                               allwinner,pins = "PA4", "PA5";
+                               allwinner,function = "uart0";
+                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       };
+ 
+                       uart1_pins_a: uart1@0 {
+                               allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+                               allwinner,function = "uart1";
+                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       };
                };
  
 -              ahb_rst: reset@01c202c0 {
 -                      #reset-cells = <1>;
 -                      compatible = "allwinner,sun6i-a31-ahb1-reset";
 -                      reg = <0x01c202c0 0xc>;
 -              };
 -
 -              apb1_rst: reset@01c202d0 {
 -                      #reset-cells = <1>;
 -                      compatible = "allwinner,sun6i-a31-clock-reset";
 -                      reg = <0x01c202d0 0x4>;
 -              };
 -
 -              apb2_rst: reset@01c202d8 {
 -                      #reset-cells = <1>;
 -                      compatible = "allwinner,sun6i-a31-clock-reset";
 -                      reg = <0x01c202d8 0x4>;
 -              };
 -
                timer@01c20c00 {
                        compatible = "allwinner,sun4i-a10-timer";
                        reg = <0x01c20c00 0xa0>;
 
        .smp_boot_secondary     = kona_boot_secondary,
  };
  CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
-                       &bcm_smp_ops);
+                       &kona_smp_ops);
  
 +static const struct smp_operations bcm23550_smp_ops __initconst = {
 +      .smp_boot_secondary     = bcm23550_boot_secondary,
 +};
 +CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
 +                      &bcm23550_smp_ops);
 +
  static const struct smp_operations nsp_smp_ops __initconst = {
        .smp_prepare_cpus       = bcm_smp_prepare_cpus,
        .smp_boot_secondary     = nsp_boot_secondary,