return 0;
 }
 
+static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
+{
+       /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
+       bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
+
+       /* Cut master bias current by 2% to compensate for RC_CAL offset */
+       bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
+
+       /* Improve hybrid leakage */
+       bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
+
+       /* Change rx_on_tune 8 to 0xf */
+       bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
+
+       /* Change 100Tx EEE bandwidth */
+       bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
+
+       /* Enable ffe zero detection for Vitesse interoperability */
+       bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
+
+       r_rc_cal_reset(phydev);
+
+       return 0;
+}
+
 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
 {
        u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
        u8 count;
        int ret = 0;
 
+       /* Newer devices have moved the revision information back into a
+        * standard location in MII_PHYS_ID[23]
+        */
+       if (rev == 0)
+               rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
+
        pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
                     phydev_name(phydev), phydev->drv->name, rev, patch);
 
        case 0x10:
                ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
                break;
+       case 0x01:
+               ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
+               break;
        default:
                break;
        }