Revert "drm/amd/display: dml2 soc dscclk use DPM table clk setting"

[why]
this dscclk use DCN defined per DPM level will cause a DCFCLK increase.
needs to follow up.

This reverts commit 15b959534a39530a21d378190557cc8d1eab7b09

Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 70c39df62533e55a67f4a1f5f231bc16938d7ffa..2061d43b92e1b99467cd68700a4f1280f5c778e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -590,11 +590,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
                        p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
                        p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
 
+                       p->out_states->state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0;
                        p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;
                        p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;
 
                        /* Dependent states. */
-                       p->out_states->state_array[i].dscclk_mhz = p->in_states->state_array[i].dscclk_mhz;
                        p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;
                        p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;
                        p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;