sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
                        if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
                                break;
-                       msleep(10);
+                       usleep_range(10000, 20000);
                }
 
                if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
 
 
                /* Release the semaphore */
                ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
-               /* Delay obtaining semaphore again to allow FW access */
-               msleep(hw->eeprom.semaphore_delay);
+               /*
+                * Delay obtaining semaphore again to allow FW access,
+                * semaphore_delay is in ms usleep_range needs us.
+                */
+               usleep_range(hw->eeprom.semaphore_delay * 1000,
+                            hw->eeprom.semaphore_delay * 2000);
 
                /* Now restart DSP by setting Restart_AN and clearing LMS */
                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
 
                /* Wait for AN to leave state 0 */
                for (i = 0; i < 10; i++) {
-                       msleep(4);
+                       usleep_range(4000, 8000);
                        reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
                        if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
                                break;
                if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
                                   IXGBE_FDIRCTRL_INIT_DONE)
                        break;
-               msleep(1);
+               usleep_range(1000, 2000);
        }
        if (i >= IXGBE_FDIR_INIT_DONE_POLL)
                hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
                if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
                                   IXGBE_FDIRCTRL_INIT_DONE)
                        break;
-               msleep(1);
+               usleep_range(1000, 2000);
        }
        if (i >= IXGBE_FDIR_INIT_DONE_POLL)
                hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
 
        reg_val &= ~(IXGBE_RXCTRL_RXEN);
        IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
        IXGBE_WRITE_FLUSH(hw);
-       msleep(2);
+       usleep_range(2000, 4000);
 
        /* Clear interrupt mask to stop from interrupts being generated */
        IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
 
        hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 
-       /* Delay before attempt to obtain semaphore again to allow FW access */
-       msleep(hw->eeprom.semaphore_delay);
+       /*
+        * Delay before attempt to obtain semaphore again to allow FW
+        * access. semaphore_delay is in ms we need us for usleep_range
+        */
+       usleep_range(hw->eeprom.semaphore_delay * 1000,
+                    hw->eeprom.semaphore_delay * 2000);
 }
 
 /**
                 * thread currently using resource (swmask)
                 */
                ixgbe_release_eeprom_semaphore(hw);
-               msleep(5);
+               usleep_range(5000, 10000);
                timeout--;
        }
 
                autoc_reg |= IXGBE_AUTOC_AN_RESTART;
                autoc_reg |= IXGBE_AUTOC_FLU;
                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
-               msleep(10);
+               usleep_range(10000, 20000);
        }
 
        led_reg &= ~IXGBE_LED_MODE_MASK(index);
 
         */
        if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
                while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
-                       msleep(1);
+                       usleep_range(1000, 2000);
 
                ixgbe_fcoe_setapp(adapter, up);
 
 
        }
 
        while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
-               msleep(1);
+               usleep_range(1000, 2000);
 
        if (!netif_running(adapter->netdev)) {
                for (i = 0; i < adapter->num_tx_queues; i++)
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
-       msleep(10);
+       usleep_range(10000, 20000);
 
        /* Test each interrupt */
        for (; i < 10; i++) {
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
-                       msleep(10);
+                       usleep_range(10000, 20000);
 
                        if (adapter->test_icr & mask) {
                                *data = 3;
                adapter->test_icr = 0;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
-               msleep(10);
+               usleep_range(10000, 20000);
 
                if (!(adapter->test_icr &mask)) {
                        *data = 4;
                                        ~mask & 0x00007FFF);
                        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
                                        ~mask & 0x00007FFF);
-                       msleep(10);
+                       usleep_range(10000, 20000);
 
                        if (adapter->test_icr) {
                                *data = 5;
 
        /* Disable all the interrupts */
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
-       msleep(10);
+       usleep_range(10000, 20000);
 
        /* Unhook test interrupt handler */
        free_irq(irq, netdev);
        reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
        IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
        IXGBE_WRITE_FLUSH(&adapter->hw);
-       msleep(10);
+       usleep_range(10000, 20000);
 
        /* Disable Atlas Tx lanes; re-enabled in reset path */
        if (hw->mac.type == ixgbe_mac_82598EB) {
 
 
        /* poll to verify queue is enabled */
        do {
-               msleep(1);
+               usleep_range(1000, 2000);
                txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
        } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
        if (!wait_loop)
                return;
 
        do {
-               msleep(1);
+               usleep_range(1000, 2000);
                rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
        } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
 
 {
        WARN_ON(in_interrupt());
        while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
-               msleep(1);
+               usleep_range(1000, 2000);
        ixgbe_down(adapter);
        /*
         * If SR-IOV enabled then wait a bit before bringing the adapter
                /* this call also flushes the previous write */
                ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
 
-       msleep(10);
+       usleep_range(10000, 20000);
 
        netif_tx_stop_all_queues(netdev);
 
 
                                     &phy_data);
                if ((phy_data & MDIO_CTRL1_RESET) == 0)
                        break;
-               msleep(10);
+               usleep_range(10000, 20000);
        }
 
        if ((phy_data & MDIO_CTRL1_RESET) != 0) {
                case IXGBE_DELAY_NL:
                        data_offset++;
                        hw_dbg(hw, "DELAY: %d MS\n", edata);
-                       msleep(edata);
+                       usleep_range(edata * 1000, edata * 2000);
                        break;
                case IXGBE_DATA_NL:
                        hw_dbg(hw, "DATA:\n");
 
                         * resource (swmask)
                         */
                        ixgbe_release_swfw_sync_semaphore(hw);
-                       msleep(5);
+                       usleep_range(5000, 10000);
                }
        }
 
                }
        }
 
-       msleep(5);
+       usleep_range(5000, 10000);
        return 0;
 }
 
        IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 
        ixgbe_release_swfw_sync_semaphore(hw);
-       msleep(5);
+       usleep_range(5000, 10000);
 }
 
 /**