Not needed since the driver split.
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
                        iwlagn_mod_params.num_of_queues;
 
        priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
-       priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
        priv->hw_params.scd_bc_tbls_size =
                        priv->cfg->base_params->num_of_queues *
                        sizeof(struct iwlagn_scd_bc_tbl);
 
                        iwlagn_mod_params.num_of_queues;
 
        priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
-       priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
        priv->hw_params.scd_bc_tbls_size =
                priv->cfg->base_params->num_of_queues *
                sizeof(struct iwlagn_scd_bc_tbl);
 
                        iwlagn_mod_params.num_of_queues;
 
        priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
-       priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
        priv->hw_params.scd_bc_tbls_size =
                        priv->cfg->base_params->num_of_queues *
                        sizeof(struct iwlagn_scd_bc_tbl);
                        iwlagn_mod_params.num_of_queues;
 
        priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
-       priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
        priv->hw_params.scd_bc_tbls_size =
                        priv->cfg->base_params->num_of_queues *
                        sizeof(struct iwlagn_scd_bc_tbl);
 
                        iwlagn_mod_params.num_of_queues;
 
        priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
-       priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
        priv->hw_params.scd_bc_tbls_size =
                        priv->cfg->base_params->num_of_queues *
                        sizeof(struct iwlagn_scd_bc_tbl);
 
                       priv->scd_bc_tbls.dma >> 10);
 
        /* Enable DMA channel */
-       for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
+       for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
                iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
                                FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 
 /**
  * struct iwl_hw_params
  * @max_txq_num: Max # Tx queues supported
- * @dma_chnl_num: Number of Tx DMA/FIFO channels
  * @scd_bc_tbls_size: size of scheduler byte count tables
  * @tfd_size: TFD size
  * @tx/rx_chains_num: Number of TX/RX chains
  */
 struct iwl_hw_params {
        u8 max_txq_num;
-       u8 dma_chnl_num;
        u16 scd_bc_tbls_size;
        u32 tfd_size;
        u8  tx_chains_num;
 
 #define FH_TCSR_UPPER_BOUND  (FH_MEM_LOWER_BOUND + 0xE60)
 
 /* Find Control/Status reg for given Tx DMA/FIFO channel */
-#define FH50_TCSR_CHNL_NUM                            (8)
+#define FH_TCSR_CHNL_NUM                            (8)
 
 /* TCSR: tx_config register values */
 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl)      \
 
        iwlagn_txq_set_sched(priv, 0);
 
        /* Stop each Tx DMA channel, and wait for it to be idle */
-       for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
+       for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
                iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
                if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
                                    FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),