cxl/pci: Add trace logging for CXL PCIe Port RAS errors

The CXL drivers use kernel trace functions for logging endpoint and
Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
Upstream Switch Ports.

Introduce trace logging functions for both RAS correctable and
uncorrectable errors specific to CXL PCIe Ports. Use them to trace
FW-First Protocol errors.

Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20250310223839.31342-3-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 91273af6ccbc7ed7af98ed2ef9fcb288a3747c27..485a831695c7052b3c5ef7302801b6fb75a6af71 100644 (file)
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -7,6 +7,30 @@
 #include <cxlmem.h>
 #include "trace.h"
 
+static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,
+                                             struct cxl_ras_capability_regs ras_cap)
+{
+       u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
+
+       trace_cxl_port_aer_correctable_error(&pdev->dev, status);
+}
+
+static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,
+                                               struct cxl_ras_capability_regs ras_cap)
+{
+       u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
+       u32 fe;
+
+       if (hweight32(status) > 1)
+               fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
+                                  ras_cap.cap_control));
+       else
+               fe = status;
+
+       trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,
+                                              ras_cap.header_log);
+}
+
 static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,
                                  struct cxl_ras_capability_regs ras_cap)
 {
@@ -49,12 +73,25 @@ static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
                pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,
                                            data->prot_err.agent_addr.bus,
                                            devfn);
+       int port_type;
 
        if (!pdev)
                return;
 
        guard(device)(&pdev->dev);
 
+       port_type = pci_pcie_type(pdev);
+       if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
+           port_type == PCI_EXP_TYPE_DOWNSTREAM ||
+           port_type == PCI_EXP_TYPE_UPSTREAM) {
+               if (data->severity == AER_CORRECTABLE)
+                       cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);
+               else
+                       cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);
+
+               return;
+       }
+
        if (data->severity == AER_CORRECTABLE)
                cxl_cper_trace_corr_prot_err(pdev, data->ras_cap);
        else

diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index cea706b683b5294f080c743c6bcd75325d0e5d1f..342ae8d50f325f7c4fb8446238a4b413c346210b 100644 (file)
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -48,6 +48,34 @@
        { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" }                         \
 )
 
+TRACE_EVENT(cxl_port_aer_uncorrectable_error,
+       TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
+       TP_ARGS(dev, status, fe, hl),
+       TP_STRUCT__entry(
+               __string(device, dev_name(dev))
+               __string(host, dev_name(dev->parent))
+               __field(u32, status)
+               __field(u32, first_error)
+               __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
+       ),
+       TP_fast_assign(
+               __assign_str(device);
+               __assign_str(host);
+               __entry->status = status;
+               __entry->first_error = fe;
+               /*
+                * Embed the 512B headerlog data for user app retrieval and
+                * parsing, but no need to print this in the trace buffer.
+                */
+               memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
+       ),
+       TP_printk("device=%s host=%s status: '%s' first_error: '%s'",
+                 __get_str(device), __get_str(host),
+                 show_uc_errs(__entry->status),
+                 show_uc_errs(__entry->first_error)
+       )
+);
+
 TRACE_EVENT(cxl_aer_uncorrectable_error,
        TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),
        TP_ARGS(cxlmd, status, fe, hl),
@@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
        { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" }     \
 )
 
+TRACE_EVENT(cxl_port_aer_correctable_error,
+       TP_PROTO(struct device *dev, u32 status),
+       TP_ARGS(dev, status),
+       TP_STRUCT__entry(
+               __string(device, dev_name(dev))
+               __string(host, dev_name(dev->parent))
+               __field(u32, status)
+       ),
+       TP_fast_assign(
+               __assign_str(device);
+               __assign_str(host);
+               __entry->status = status;
+       ),
+       TP_printk("device=%s host=%s status='%s'",
+                 __get_str(device), __get_str(host),
+                 show_ce_errs(__entry->status)
+       )
+);
+
 TRACE_EVENT(cxl_aer_correctable_error,
        TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),
        TP_ARGS(cxlmd, status),