supported by this device instance
 - snps,perfect-filter-entries: Number of perfect filter entries supported
                                by this device instance
+- snps,ps-speed: port selection speed that can be passed to the core when
+                PCS is supported. For example, this is used in case of SGMII
+                and MAC2MAC connection.
 - AXI BUS Mode parameters: below the list of all the parameters to program the
                           AXI register inside the DMA module:
        - snps,lpi_en: enable Low Power Interface
 
        unsigned int rx_csum;
        unsigned int pcs;
        unsigned int pmt;
+       unsigned int ps;
 };
 
 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 
        if (mtu > 2000)
                value |= GMAC_CONTROL_JE;
 
+       if (hw->ps) {
+               value |= GMAC_CONTROL_TE;
+
+               if (hw->ps == SPEED_1000) {
+                       value &= ~GMAC_CONTROL_PS;
+               } else {
+                       value |= GMAC_CONTROL_PS;
+
+                       if (hw->ps == SPEED_10)
+                               value &= ~GMAC_CONTROL_FES;
+                       else
+                               value |= GMAC_CONTROL_FES;
+               }
+       }
+
        writel(value, ioaddr + GMAC_CONTROL);
 
        /* Mask GMAC interrupts */
 
        if (mtu > 2000)
                value |= GMAC_CONFIG_JE;
 
+       if (hw->ps) {
+               value |= GMAC_CONFIG_TE;
+
+               if (hw->ps == SPEED_1000) {
+                       value &= ~GMAC_CONFIG_PS;
+               } else {
+                       value |= GMAC_CONFIG_PS;
+
+                       if (hw->ps == SPEED_10)
+                               value &= ~GMAC_CONFIG_FES;
+                       else
+                               value |= GMAC_CONFIG_FES;
+               }
+       }
+
        writel(value, ioaddr + GMAC_CONFIG);
 
        /* Mask GMAC interrupts */
 
                spin_lock(&priv->lock);
 
                if (priv->hw->mac->pcs_ctrl_ane)
-                       priv->hw->mac->pcs_ctrl_ane(priv->ioaddr, 1, 0, 0);
+                       priv->hw->mac->pcs_ctrl_ane(priv->ioaddr, 1,
+                                                   priv->hw->ps, 0);
 
                spin_unlock(&priv->lock);
 
 
        if (priv->plat->bus_setup)
                priv->plat->bus_setup(priv->ioaddr);
 
+       /* PS and related bits will be programmed according to the speed */
+       if (priv->hw->pcs) {
+               int speed = priv->plat->mac_port_sel_speed;
+
+               if ((speed == SPEED_10) || (speed == SPEED_100) ||
+                   (speed == SPEED_1000)) {
+                       priv->hw->ps = speed;
+               } else {
+                       dev_warn(priv->device, "invalid port speed\n");
+                       priv->hw->ps = 0;
+               }
+       }
+
        /* Initialize the MAC Core */
        priv->hw->mac->core_init(priv->hw, dev->mtu);
 
        }
 
        if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
-               priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, 0, 0);
+               priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
 
        /*  set TX ring length */
        if (priv->hw->dma->set_tx_ring_len)
 
                pr_warn("force_sf_dma_mode is ignored if force_thresh_dma_mode is set.");
        }
 
+       of_property_read_u32(np, "snps,ps-speed", &plat->mac_port_sel_speed);
+
        plat->axi = stmmac_axi_setup(pdev);
 
        return plat;
 
        struct stmmac_axi *axi;
        int has_gmac4;
        bool tso_en;
+       int mac_port_sel_speed;
 };
 #endif