--- /dev/null
+ # SPDX-License-Identifier: GPL-2.0-only
+ %YAML 1.2
+ ---
+ $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
+ $schema: http://devicetree.org/meta-schemas/core.yaml#
+ 
+ title: Qualcomm's USB HS PHY binding description
+ 
+ maintainers:
+   - Bjorn Andersson <bjorn.andersson@linaro.org>
+ 
+ if:
+   properties:
+     compatible:
+       contains:
+         const: qcom,usb-hs-phy-apq8064
+   then:
+     properties:
+       resets:
+         maxItems: 1
+ 
+       reset-names:
+         const: por
+ 
+   else:
+     properties:
+       resets:
+         minItems: 2
+         maxItems: 2
+ 
+       reset-names:
+         items:
+           - const: phy
+           - const: por
+ 
+ properties:
+   compatible:
+     items:
+       - enum:
+           - qcom,usb-hs-phy-apq8064
++          - qcom,usb-hs-phy-msm8226
+           - qcom,usb-hs-phy-msm8916
+           - qcom,usb-hs-phy-msm8974
+       - const: qcom,usb-hs-phy
+ 
+   clocks:
+     minItems: 2
+     maxItems: 2
+ 
+   clock-names:
+     maxItems: 2
+     contains:
+       items:
+         - const: ref
+         - const: sleep
+ 
+   resets: true
+ 
+   reset-names: true
+ 
+   v1p8-supply: true
+ 
+   v3p3-supply: true
+ 
+   extcon: true
+ 
+   "#phy-cells":
+     const: 0
+ 
+   qcom,init-seq:
+     $ref: /schemas/types.yaml#/definitions/uint8-matrix
+     description: >
+       Sequence of ULPI address and value pairs to
+       program into the ULPI_EXT_VENDOR_SPECIFIC area.
+       This is related to Device Mode Eye Diagram test.
+     maxItems: 32 # no hard limit
+     items:
+       items:
+         - description: >
+             the address is offset from the ULPI_EXT_VENDOR_SPECIFIC address
+         - description: value
+ 
+ required:
+   - clocks
+   - clock-names
+   - resets
+   - reset-names
+   - "#phy-cells"
+ 
+ additionalProperties: false
+ 
+ examples:
+   - |
+     otg: usb-controller {
+       ulpi {
+         phy {
+           compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
+           #phy-cells = <0>;
+           clocks = <&clk 0>, <&clk 258>;
+           clock-names = "ref", "sleep";
+           resets = <&gcc 10>, <&otg 0>;
+           reset-names = "phy", "por";
+           v3p3-supply = <&pm8941_l24>;
+           v1p8-supply = <&pm8941_l6>;
+           extcon = <&smbb>;
+           qcom,init-seq = /bits/ 8 <0x1 0x63>;
+         };
+       };
+     };
 
  S:    Maintained
  F:    drivers/net/ethernet/dlink/sundance.c
  
++SUNPLUS OCOTP DRIVER
++M:    Vincent Shih <vincent.sunplus@gmail.com>
++S:    Maintained
++F:    Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
++F:    drivers/nvmem/sunplus-ocotp.c
++
  SUNPLUS RTC DRIVER
  M:    Vincent Shih <vincent.sunplus@gmail.com>
  L:    linux-rtc@vger.kernel.org
  F:    drivers/ptp/ptp_vmw.c
  
  VMWARE VMCI DRIVER
- M:    Jorgen Hansen <jhansen@vmware.com>
+ M:    Bryan Tan <bryantan@vmware.com>
+ M:    Rajesh Jalisatgi <rjalisatgi@vmware.com>
  M:    Vishnu Dasa <vdasa@vmware.com>
 +R:    VMware PV-Drivers Reviewers <pv-drivers@vmware.com>
  L:    linux-kernel@vger.kernel.org
 -L:    pv-drivers@vmware.com (private)
  S:    Maintained
  F:    drivers/misc/vmw_vmci/
  
 
          Enable this to add support for the PCIE PHY as found on
          i.MX8M family of SOCs.
  
 +config PHY_FSL_LYNX_28G
 +      tristate "Freescale Layerscape Lynx 28G SerDes PHY support"
 +      depends on OF
 +      select GENERIC_PHY
 +      help
 +        Enable this to add support for the Lynx SerDes 28G PHY as
 +        found on NXP's Layerscape platforms such as LX2160A.
 +        Used to change the protocol running on SerDes lanes at runtime.
 +        Only useful for a restricted set of Ethernet protocols.
++
+ endif