x86/smp: Provide topology_is_primary_thread()

If the CPU is supporting SMT then the primary thread can be found by
checking the lower APIC ID bits for zero. smp_num_siblings is used to build
the mask for the APIC ID bits which need to be taken into account.

This uses the MPTABLE or ACPI/MADT supplied APIC ID, which can be different
than the initial APIC ID in CPUID. But according to AMD the lower bits have
to be consistent. Intel gave a tentative confirmation as well.

Preparatory patch to support disabling SMT at boot/runtime.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Orabug: 28220674
CVE: CVE-2018-3620

(cherry picked from commit 6a4d2657e048f096c7ffcad254010bd94891c8c0)

Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Conflicts:
	arch/x86/include/asm/apic.h
	arch/x86/include/asm/topology.h
	arch/x86/kernel/apic/apic.c
	arch/x86/kernel/smpboot.c
Contextual

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 69078eb679bb14e15c1686007a6bbc8c460bd7b6..1349b2842a55ca52329fe9a637e941f0e15ceda3 100644 (file)
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -115,6 +115,12 @@ static inline bool apic_is_x2apic_enabled(void)
        return msr & X2APIC_ENABLE;
 }
 
+#ifdef CONFIG_SMP
+bool apic_id_is_primary_thread(unsigned int id);
+#else
+static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
+#endif
+
 #ifdef CONFIG_X86_X2APIC
 /*
  * Make previous memory operations globally visible before

diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 0e8f04f2c26fda3935093b7040dac783e621d71b..bf9b53421a6f791d4d75837fc64c9f9f5156594a 100644 (file)
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -122,6 +122,12 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu);
 #define topology_physical_package_id(cpu)      (cpu_data(cpu).phys_proc_id)
 #define topology_core_id(cpu)                  (cpu_data(cpu).cpu_core_id)
 
+#ifdef CONFIG_SMP
+bool topology_is_primary_thread(unsigned int cpu);
+#else
+static inline bool topology_is_primary_thread(unsigned int cpu) { return true; }
+#endif
+
 #ifdef ENABLE_TOPO_DEFINES
 #define topology_core_cpumask(cpu)             (per_cpu(cpu_core_map, cpu))
 #define topology_thread_cpumask(cpu)           (per_cpu(cpu_sibling_map, cpu))

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b69e79d707e33b6c28bb72f94a4722b8cf0dd5e5..e900f44a36f79a0d3fae76876bb1deb36bc672a9 100644 (file)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1986,6 +1986,21 @@ void disconnect_bsp_APIC(int virt_wire_setup)
        apic_write(APIC_LVT1, value);
 }
 
+/**
+ * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
+ * @id:        APIC ID to check
+ */
+bool apic_id_is_primary_thread(unsigned int apicid)
+{
+       u32 mask;
+
+       if (smp_num_siblings == 1)
+               return true;
+       /* Isolate the SMT bit(s) in the APICID and check for 0 */
+       mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
+       return !(apicid & mask);
+}
+
 int generic_processor_info(int apicid, int version)
 {
        int cpu, max = nr_cpu_ids;

diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 05520fb819f6e2a06446864c31e3250732209181..76c42a0d26c400393ffde0375ec8814b684bd6fc 100644 (file)
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -270,6 +270,15 @@ static void notrace start_secondary(void *unused)
        cpu_startup_entry(CPUHP_ONLINE);
 }
 
+/**
+ * topology_is_primary_thread - Check whether CPU is the primary SMT thread
+ * @cpu:       CPU to check
+ */
+bool topology_is_primary_thread(unsigned int cpu)
+{
+       return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
+}
+
 void __init smp_store_boot_cpu_info(void)
 {
        int id = 0; /* CPU 0 */