drm/xe/xe2_lpg: Introduce performance guide changes

Add performance guide changes to Xe2_LPG.

BSpec: 72161
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240123050552.2250699-2-shekhar.chauhan@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 0d4bfc35ff37efba6760aa9253b0b8340e676bc6..cd27480f6486268a7dd07d38afedae9668bbfc24 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -144,6 +144,9 @@
 
 #define GSCPSMI_BASE                           XE_REG(0x880c)
 
+#define CCCHKNREG1                             XE_REG_MCR(0x8828)
+#define   ENCOMPPERFFIX                                REG_BIT(18)
+
 /* Fuse readout registers for GT */
 #define XEHP_FUSE4                             XE_REG(0x9114)
 #define   CFEG_WMTP_DISABLE                    REG_BIT(20)
@@ -289,6 +292,9 @@
 #define XEHP_L3NODEARBCFG                      XE_REG_MCR(0xb0b4)
 #define   XEHP_LNESPARE                                REG_BIT(19)
 
+#define L3SQCREG3                              XE_REG_MCR(0xb108)
+#define   COMPPWOVERFETCHEN                    REG_BIT(28)
+
 #define XEHP_L3SQCREG5                         XE_REG_MCR(0xb158)
 #define   L3_PWM_TIMER_INIT_VAL_MASK           REG_GENMASK(9, 0)
 

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 53ccd338fd8c0c673253ed835da339a46184bf42..5c83c75bc4978dccad0f9d8bc242a687a3739106 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -37,7 +37,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
                                   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
        },
-
+       { XE_RTP_NAME("Tuning: Compression Overfetch"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)),
+       },
+       { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
+         XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
+       },
        {}
 };