drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0

This reverts commit 871512e36f9c1c2cb4e62eb860ca0438800e4d63
due to multiple issues found.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Teeger <gateeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index c5823512147457d38425f585008941f1df21c887..d5dcc8b7728169f012f6516eaa17b6578abe7b02 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -626,21 +626,6 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s
 
        if (result) {
                unsigned int lowest_state_idx = s->mode_support_params.out_lowest_state_idx;
-               double min_fclk_mhz_for_urgent_workaround = (double)dml2->config.min_fclk_for_urgent_workaround_khz / 1000.0;
-               double max_frac_urgent = (double)dml2->config.max_frac_urgent_for_min_fclk_x1000 / 1000.0;
-
-               if (min_fclk_mhz_for_urgent_workaround > 0.0 && max_frac_urgent > 0.0 &&
-                   (dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidth > max_frac_urgent ||
-                    dml2->v20.dml_core_ctx.mp.FractionOfUrgentBandwidthImmediateFlip > max_frac_urgent)) {
-                       unsigned int forced_lowest_state_idx = lowest_state_idx;
-
-                       while (forced_lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states &&
-                              dml2->v20.dml_core_ctx.states.state_array[forced_lowest_state_idx].fabricclk_mhz <= min_fclk_mhz_for_urgent_workaround) {
-                               forced_lowest_state_idx += 1;
-                       }
-                       lowest_state_idx = forced_lowest_state_idx;
-               }
-
                out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000;
                out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported;
                if (in_dc->config.use_default_clock_table &&

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index 6e3d52eb45c7ce13fe43e475e051373f6e07402f..023325e8f6e22f735ddf0daca0e42921cc750fe9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -237,8 +237,6 @@ struct dml2_configuration_options {
        bool use_clock_dc_limits;
        bool gpuvm_enable;
        struct dml2_soc_bb *bb_from_dmub;
-       int max_frac_urgent_for_min_fclk_x1000;
-       int min_fclk_for_urgent_workaround_khz;
 };
 
 /*

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 1ce0f9ecff9cf0d777954abcb593f807a068dd83..ddf251901fb331972bb7aaa1339c2cc44c75701e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -2153,8 +2153,6 @@ static bool dcn35_resource_construct(
 
        dc->dml2_options.max_segments_per_hubp = 24;
        dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
-       dc->dml2_options.max_frac_urgent_for_min_fclk_x1000 = 900;
-       dc->dml2_options.min_fclk_for_urgent_workaround_khz = 400 * 1000;
 
        if (dc->config.sdpif_request_limit_words_per_umc == 0)
                dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/