perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09

Some HiSilicon SMMU PMCG suffers the erratum 162001900 that the PMU
disable control sometimes fail to disable the counters. This will lead
to error or inaccurate data since before we enable the counters the
counter's still counting for the event used in last perf session.

This patch tries to fix this by hardening the global disable process.
Before disable the PMU, writing an invalid event type (0xffff) to
focibly stop the counters. Correspondingly restore each events on
pmu::pmu_enable().

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20230814124012.58013-1-yangyicong@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 496cdca5cb99002837a87b83834bce0d9fc0d60a..d54626cfcbda9539d47666af4b2199043d36e62b 100644 (file)
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -195,6 +195,9 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
+| Hisilicon      | Hip08 SMMU PMCG | #162001900      | N/A                         |
+|                | Hip09 SMMU PMCG |                 |                             |
++----------------+-----------------+-----------------+-----------------------------+
 +----------------+-----------------+-----------------+-----------------------------+
 | Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 +----------------+-----------------+-----------------+-----------------------------+

diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 3631230a61c8f52bc77334d5344b5b235eb405a2..2c1640fd2b165a95b1da43c977808466e4163d46 100644 (file)
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -1711,7 +1711,10 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res,
 static struct acpi_platform_list pmcg_plat_info[] __initdata = {
        /* HiSilicon Hip08 Platform */
        {"HISI  ", "HIP08   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
-        "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08},
+        "Erratum #162001800, Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP08},
+       /* HiSilicon Hip09 Platform */
+       {"HISI  ", "HIP09   ", 0, ACPI_SIG_IORT, greater_than_or_equal,
+        "Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
        { }
 };
 

diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 25a269d431e455e8fbf88cd8d8e4b7370ce65216..0e17c57ddb876d9640da443d714b3803950ea477 100644 (file)
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -115,6 +115,7 @@
 #define SMMU_PMCG_PA_SHIFT              12
 
 #define SMMU_PMCG_EVCNTR_RDONLY         BIT(0)
+#define SMMU_PMCG_HARDEN_DISABLE        BIT(1)
 
 static int cpuhp_state_num;
 
@@ -159,6 +160,20 @@ static inline void smmu_pmu_enable(struct pmu *pmu)
        writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
 }
 
+static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
+                                      struct perf_event *event, int idx);
+
+static inline void smmu_pmu_enable_quirk_hip08_09(struct pmu *pmu)
+{
+       struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
+       unsigned int idx;
+
+       for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
+               smmu_pmu_apply_event_filter(smmu_pmu, smmu_pmu->events[idx], idx);
+
+       smmu_pmu_enable(pmu);
+}
+
 static inline void smmu_pmu_disable(struct pmu *pmu)
 {
        struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
@@ -167,6 +182,22 @@ static inline void smmu_pmu_disable(struct pmu *pmu)
        writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
 }
 
+static inline void smmu_pmu_disable_quirk_hip08_09(struct pmu *pmu)
+{
+       struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
+       unsigned int idx;
+
+       /*
+        * The global disable of PMU sometimes fail to stop the counting.
+        * Harden this by writing an invalid event type to each used counter
+        * to forcibly stop counting.
+        */
+       for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
+               writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
+
+       smmu_pmu_disable(pmu);
+}
+
 static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
                                              u32 idx, u64 value)
 {
@@ -765,7 +796,10 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
        switch (model) {
        case IORT_SMMU_V3_PMCG_HISI_HIP08:
                /* HiSilicon Erratum 162001800 */
-               smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
+               smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY | SMMU_PMCG_HARDEN_DISABLE;
+               break;
+       case IORT_SMMU_V3_PMCG_HISI_HIP09:
+               smmu_pmu->options |= SMMU_PMCG_HARDEN_DISABLE;
                break;
        }
 
@@ -890,6 +924,16 @@ static int smmu_pmu_probe(struct platform_device *pdev)
        if (!dev->of_node)
                smmu_pmu_get_acpi_options(smmu_pmu);
 
+       /*
+        * For platforms suffer this quirk, the PMU disable sometimes fails to
+        * stop the counters. This will leads to inaccurate or error counting.
+        * Forcibly disable the counters with these quirk handler.
+        */
+       if (smmu_pmu->options & SMMU_PMCG_HARDEN_DISABLE) {
+               smmu_pmu->pmu.pmu_enable = smmu_pmu_enable_quirk_hip08_09;
+               smmu_pmu->pmu.pmu_disable = smmu_pmu_disable_quirk_hip08_09;
+       }
+
        /* Pick one CPU to be the preferred one to use */
        smmu_pmu->on_cpu = raw_smp_processor_id();
        WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu)));

diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
index ee7cb6aaff718114c905e02e26f6c4c3dca0a869..1cb65592c95dd3376e6ca66b629bb69bb11a5dd7 100644 (file)
--- a/include/linux/acpi_iort.h
+++ b/include/linux/acpi_iort.h
@@ -21,6 +21,7 @@
  */
 #define IORT_SMMU_V3_PMCG_GENERIC        0x00000000 /* Generic SMMUv3 PMCG */
 #define IORT_SMMU_V3_PMCG_HISI_HIP08     0x00000001 /* HiSilicon HIP08 PMCG */
+#define IORT_SMMU_V3_PMCG_HISI_HIP09     0x00000002 /* HiSilicon HIP09 PMCG */
 
 int iort_register_domain_token(int trans_id, phys_addr_t base,
                               struct fwnode_handle *fw_node);