]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
coresight: Add label sysfs node support
authorMao Jinlong <quic_jinlmao@quicinc.com>
Sat, 16 Aug 2025 07:25:29 +0000 (00:25 -0700)
committerSuzuki K Poulose <suzuki.poulose@arm.com>
Tue, 23 Sep 2025 13:14:13 +0000 (14:14 +0100)
For some coresight components like CTI and TPDM, there could be
numerous of them. From the node name, we can only get the type and
register address of the component. We can't identify the HW or the
system the component belongs to. Add label sysfs node support for
showing the intuitive name of the device.

Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250816072529.3716968-3-quic_jinlmao@quicinc.com
Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel
Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
drivers/hwtracing/coresight/coresight-sysfs.c

index a97b70f588da8b41e3395636037d63a0f30cf78f..a2aef7f5a6d74c3ba4d9cd32b1b47e4f8506598e 100644 (file)
@@ -239,3 +239,9 @@ Date:               March 2020
 KernelVersion: 5.7
 Contact:       Mike Leach or Mathieu Poirier
 Description:   (Write) Clear all channel / trigger programming.
+
+What:           /sys/bus/coresight/devices/<cti-name>/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index 0830661ef6568445eeaa22ea7ad98c8e7f0a8a7f..321e3ee1fc9d5898d28b83d08b9715268a5d8b30 100644 (file)
@@ -13,3 +13,9 @@ KernelVersion:        6.14
 Contact:       Mao Jinlong <quic_jinlmao@quicinc.com>
 Description:   (R) Show the trace ID that will appear in the trace stream
                coming from this trace entity.
+
+What:           /sys/bus/coresight/devices/dummy_source<N>/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index 9a383f6a74ebe10cd8991d8493ac931f510b0c07..f305269496872524d073b2e9194b587f0e4b4f85 100644 (file)
@@ -19,6 +19,12 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
                into the Trace RAM following the trigger event is equal to the
                value stored in this register+1 (from ARM ETB-TRM).
 
+What:           /sys/bus/coresight/devices/<memory_map>.etb/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
+
 What:          /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
 Date:          March 2016
 KernelVersion: 4.7
index 271b57c571aa5c3f96dc8b93c4d1c095544c4c97..245c322c91f1fe1ee9163427c269c492c85fcb07 100644 (file)
@@ -251,6 +251,12 @@ KernelVersion:     4.4
 Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (RO) Holds the cpu number this tracer is affined to.
 
+What:           /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
+
 What:          /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
 Date:          September 2015
 KernelVersion: 4.4
index a0425d70d0096495c418b4692d8b3fae57e64f65..6f19a6a5f2e187be4e0648298576a4b8363fe88f 100644 (file)
@@ -329,6 +329,12 @@ Contact:   Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (RW) Access the selected single show PE comparator control
                register.
 
+What:           /sys/bus/coresight/devices/etm<N>/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
+
 What:          /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
 Date:          April 2015
 KernelVersion: 4.01
index d75acda5e1b38469f7e4afc189a3aa4f715d16c7..86938e9bbcdec67c44922c7bf374d24482ad54a8 100644 (file)
@@ -10,3 +10,9 @@ Date:         November 2014
 KernelVersion: 3.19
 Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (RW) Defines input port priority order.
+
+What:           /sys/bus/coresight/devices/<memory_map>.funnel/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index 53e1f4815d64314e6d6181978fa2ecbd77f5b9db..848e2ffc1480cc7d92d3d9d6d198486fec10638a 100644 (file)
@@ -51,3 +51,9 @@ KernelVersion:        4.7
 Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (RW) Holds the trace ID that will appear in the trace stream
                coming from this trace entity.
+
+What:           /sys/bus/coresight/devices/<memory_map>.stm/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index 339cec3b2f1a6928024e7dfa96b5a36166f5fda1..55e298b9c4a4b06179a2a9dc90483a8363cdacd0 100644 (file)
@@ -107,3 +107,9 @@ Contact:    Anshuman Khandual <anshuman.khandual@arm.com>
 Description:   (RW) Current Coresight TMC-ETR buffer mode selected. But user could
                only provide a mode which is supported for a given ETR device. This
                file is available only for TMC ETR devices.
+
+What:           /sys/bus/coresight/devices/<memory_map>.tmc/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index a341b08ae70bf344c62b11b18775cc295a6f43bd..98f1c654502754a41e1589585e3848b4871b73cc 100644 (file)
@@ -272,3 +272,9 @@ KernelVersion       6.15
 Contact:       Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
 Description:
                (RW) Set/Get the enablement of the individual lane.
+
+What:           /sys/bus/coresight/devices/<tpdm-name>/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index ad3bbc6fa751d57cec6fba5397c7c183ffbe2375..8a4b749ed26e90b54cb99ea34d61b088ce9af99f 100644 (file)
@@ -12,3 +12,9 @@ Contact:      Anshuman Khandual <anshuman.khandual@arm.com>
 Description:   (Read) Shows if TRBE updates in the memory are with access
                and dirty flag updates as well. This value is fetched from
                the TRBIDR register.
+
+What:           /sys/bus/coresight/devices/trbe<cpu>/label
+Date:           Aug 2025
+KernelVersion   6.18
+Contact:        Mao Jinlong <quic_jinlmao@quicinc.com>
+Description:    (Read) Show hardware context information of device.
index feadaf065b5318c8426aa53420b8e5f67a258683..5e52324aa9ac7b3de9379bc3f2b349a2cdea83c2 100644 (file)
@@ -7,6 +7,7 @@
 #include <linux/device.h>
 #include <linux/idr.h>
 #include <linux/kernel.h>
+#include <linux/property.h>
 
 #include "coresight-priv.h"
 #include "coresight-trace-id.h"
@@ -371,17 +372,81 @@ static ssize_t enable_source_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(enable_source);
 
+static ssize_t label_show(struct device *dev,
+               struct device_attribute *attr, char *buf)
+{
+
+       const char *str;
+       int ret;
+
+       ret = fwnode_property_read_string(dev_fwnode(dev), "label", &str);
+       if (ret == 0)
+               return sysfs_emit(buf, "%s\n", str);
+       else
+               return ret;
+}
+static DEVICE_ATTR_RO(label);
+
+static umode_t label_is_visible(struct kobject *kobj,
+                                  struct attribute *attr, int n)
+{
+       struct device *dev = kobj_to_dev(kobj);
+
+       if (attr == &dev_attr_label.attr) {
+               if (fwnode_property_present(dev_fwnode(dev), "label"))
+                       return attr->mode;
+               else
+                       return 0;
+       }
+
+       return attr->mode;
+}
+
 static struct attribute *coresight_sink_attrs[] = {
        &dev_attr_enable_sink.attr,
+       &dev_attr_label.attr,
        NULL,
 };
-ATTRIBUTE_GROUPS(coresight_sink);
+
+static struct attribute_group coresight_sink_group = {
+       .attrs = coresight_sink_attrs,
+       .is_visible = label_is_visible,
+};
+__ATTRIBUTE_GROUPS(coresight_sink);
 
 static struct attribute *coresight_source_attrs[] = {
        &dev_attr_enable_source.attr,
+       &dev_attr_label.attr,
        NULL,
 };
-ATTRIBUTE_GROUPS(coresight_source);
+
+static struct attribute_group coresight_source_group = {
+       .attrs = coresight_source_attrs,
+       .is_visible = label_is_visible,
+};
+__ATTRIBUTE_GROUPS(coresight_source);
+
+static struct attribute *coresight_link_attrs[] = {
+       &dev_attr_label.attr,
+       NULL,
+};
+
+static struct attribute_group coresight_link_group = {
+       .attrs = coresight_link_attrs,
+       .is_visible = label_is_visible,
+};
+__ATTRIBUTE_GROUPS(coresight_link);
+
+static struct attribute *coresight_helper_attrs[] = {
+       &dev_attr_label.attr,
+       NULL,
+};
+
+static struct attribute_group coresight_helper_group = {
+       .attrs = coresight_helper_attrs,
+       .is_visible = label_is_visible,
+};
+__ATTRIBUTE_GROUPS(coresight_helper);
 
 const struct device_type coresight_dev_type[] = {
        [CORESIGHT_DEV_TYPE_SINK] = {
@@ -390,6 +455,7 @@ const struct device_type coresight_dev_type[] = {
        },
        [CORESIGHT_DEV_TYPE_LINK] = {
                .name = "link",
+               .groups = coresight_link_groups,
        },
        [CORESIGHT_DEV_TYPE_LINKSINK] = {
                .name = "linksink",
@@ -401,6 +467,7 @@ const struct device_type coresight_dev_type[] = {
        },
        [CORESIGHT_DEV_TYPE_HELPER] = {
                .name = "helper",
+               .groups = coresight_helper_groups,
        }
 };
 /* Ensure the enum matches the names and groups */