can: mcp251xfd: mcp251xfd_probe(): remove known bad combinations from errata tabe

The published errata specify the maximum allowed SPI frequency to be
max 85% of (FSYSCLK/2). So there's no need to track known bad clock
settings in the driver. As the setup of known good values is a bit
tricky, keep them.

Link: https://lore.kernel.org/r/20210128104644.2982125-4-mkl@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
index c6ccd00541523333295e5f5d004e37ce70f6d8fd..d51d11fd7064d74c492de5bc6f2703c23ad3163b 100644 (file)
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
@@ -2945,18 +2945,15 @@ static int mcp251xfd_probe(struct spi_device *spi)
         * Ensure that FSCK is less than or equal to 0.85 *
         * (FSYSCLK/2).
         *
-        * Known good and bad combinations are:
+        * Known good combinations are:
         *
-        * MCP  ext-clk SoC                     SPI                     SPI-clk         max-clk parent-clk      Status  config
+        * MCP  ext-clk SoC                     SPI                     SPI-clk         max-clk parent-clk      config
         *
-        * 2518 20 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi   8333333 Hz      83.33% 600000000 Hz    good    assigned-clocks = <&ccu CLK_SPIx>
-        * 2518 20 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi   9375000 Hz      93.75% 600000000 Hz    bad     assigned-clocks = <&ccu CLK_SPIx>
-        * 2518 40 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi  16666667 Hz      83.33% 600000000 Hz    good    assigned-clocks = <&ccu CLK_SPIx>
-        * 2518 40 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi  18750000 Hz      93.75% 600000000 Hz    bad     assigned-clocks = <&ccu CLK_SPIx>
-        * 2517 40 MHz  atmel,sama5d27          atmel,at91rm9200-spi    16400000 Hz      82.00%  82000000 Hz    good    default
-        * 2518 40 MHz  atmel,sama5d27          atmel,at91rm9200-spi    16400000 Hz      82.00%  82000000 Hz    good    default
-        * 2517 20 MHz  fsl,imx8mm              fsl,imx51-ecspi          8333333 Hz      83.33%  16666667 Hz    good    assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
-        * 2517 20 MHz  fsl,imx8mm              fsl,imx51-ecspi          9523809 Hz      95.34%  28571429 Hz    bad     assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
+        * 2518 20 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi   8333333 Hz      83.33% 600000000 Hz    assigned-clocks = <&ccu CLK_SPIx>
+        * 2518 40 MHz  allwinner,sun8i-h3      allwinner,sun8i-h3-spi  16666667 Hz      83.33% 600000000 Hz    assigned-clocks = <&ccu CLK_SPIx>
+        * 2517 40 MHz  atmel,sama5d27          atmel,at91rm9200-spi    16400000 Hz      82.00%  82000000 Hz    default
+        * 2518 40 MHz  atmel,sama5d27          atmel,at91rm9200-spi    16400000 Hz      82.00%  82000000 Hz    default
+        * 2517 20 MHz  fsl,imx8mm              fsl,imx51-ecspi          8333333 Hz      83.33%  16666667 Hz    assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
         *
         */
        priv->spi_max_speed_hz_orig = spi->max_speed_hz;