#define  SARBUNIT_CLKGATE_DIS          (1 << 5)
 #define  RCCUNIT_CLKGATE_DIS           (1 << 7)
 
+#define UNSLICE_UNIT_LEVEL_CLKGATE     _MMIO(0x9434)
+#define  VFUNIT_CLKGATE_DIS            (1 << 20)
+
 /*
  * Display engine regs
  */
 
        if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                val |= SARBUNIT_CLKGATE_DIS;
        I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
+
+       /* WaDisableVFclkgate:cnl */
+       val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
+       val |= VFUNIT_CLKGATE_DIS;
+       I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
 }
 
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)