clk: renesas: rzg2l-cpg: Use devres API to register clocks

We are using devres APIs for divider, mux and pll5 clocks so for
consistency use the devres APIs for module, fixed factor and PLL clocks.

While at it switched to clk_hw_register() instead of clk_register()
as this has been marked as deprecated interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 04b78064d4e01c3b70a67e52e0ff87bfd1bc21a3..f330805e7d8a8fae20064da2078f28974fbe3363 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        struct clk_init_data init;
        const char *parent_name;
        struct pll_clk *pll_clk;
+       int ret;
 
        parent = clks[core->parent & 0xffff];
        if (IS_ERR(parent))
@@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        pll_clk->priv = priv;
        pll_clk->type = core->type;
 
-       return clk_register(NULL, &pll_clk->hw);
+       ret = devm_clk_hw_register(dev, &pll_clk->hw);
+       if (ret)
+               return ERR_PTR(ret);
+
+       return pll_clk->hw.clk;
 }
 
 static struct clk
@@ -1102,6 +1107,7 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
        struct device *dev = priv->dev;
        unsigned int id = core->id, div = core->div;
        const char *parent_name;
+       struct clk_hw *clk_hw;
 
        WARN_DEBUG(id >= priv->num_core_clks);
        WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
@@ -1124,9 +1130,13 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
                }
 
                parent_name = __clk_get_name(parent);
-               clk = clk_register_fixed_factor(NULL, core->name,
-                                               parent_name, CLK_SET_RATE_PARENT,
-                                               core->mult, div);
+               clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name, parent_name,
+                                                          CLK_SET_RATE_PARENT,
+                                                          core->mult, div);
+               if (IS_ERR(clk_hw))
+                       clk = ERR_CAST(clk_hw);
+               else
+                       clk = clk_hw->clk;
                break;
        case CLK_TYPE_SAM_PLL:
                clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
@@ -1337,6 +1347,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
        struct clk *parent, *clk;
        const char *parent_name;
        unsigned int i;
+       int ret;
 
        WARN_DEBUG(id < priv->num_core_clks);
        WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
@@ -1380,10 +1391,13 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
        clock->priv = priv;
        clock->hw.init = &init;
 
-       clk = clk_register(NULL, &clock->hw);
-       if (IS_ERR(clk))
+       ret = devm_clk_hw_register(dev, &clock->hw);
+       if (ret) {
+               clk = ERR_PTR(ret);
                goto fail;
+       }
 
+       clk = clock->hw.clk;
        dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
        priv->clks[id] = clk;