mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER

Due to a flaw in the hardware design, the GL9750 replay timer frequently
times out when ASPM is enabled. As a result, the warning messages will
often appear in the system log when the system accesses the GL9750
PCI config. Therefore, the replay timer timeout must be masked.

Fixes: d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter ASPM L1.2")
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Kai-Heng Feng <kai.heng.geng@canonical.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231107095741.8832-2-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 044b4704d5bbcc801ec176941725ca9e0a010559..d8a991b349a823487554394a489edb7a2dd85f66 100644 (file)
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -28,6 +28,9 @@
 #define PCI_GLI_9750_PM_CTRL   0xFC
 #define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
 
+#define PCI_GLI_9750_CORRERR_MASK                              0x214
+#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT(12)
+
 #define SDHCI_GLI_9750_CFG2          0x848
 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
@@ -564,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host)
        value &= ~PCI_GLI_9750_PM_STATE;
        pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
 
+       /* mask the replay timer timeout of AER */
+       pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
+       value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
+       pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
+
        gl9750_wt_off(host);
 }