]> www.infradead.org Git - linux.git/commitdiff
riscv: sophgo: dts: add mmc controllers for SG2042 SoC
authorChen Wang <unicorn_wang@outlook.com>
Mon, 5 Aug 2024 09:19:43 +0000 (17:19 +0800)
committerChen Wang <unicorn_wang@outlook.com>
Mon, 2 Sep 2024 00:35:12 +0000 (08:35 +0800)
SG2042 has two MMC controller, one for emmc, another for sd-card.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/03ac9ec9c23bbe4c3b30271e76537bdbe5638665.1722847198.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
arch/riscv/boot/dts/sophgo/sg2042.dtsi

index 80cb017974d883a38419835c8b895103d5c1b1d6..da6596e9192e381d6e29f5a3bcf9f75981e6b389 100644 (file)
        clock-frequency = <25000000>;
 };
 
+&emmc {
+       bus-width = <4>;
+       no-sdio;
+       no-sd;
+       non-removable;
+       wp-inverted;
+       status = "okay";
+};
+
+&sd {
+       bus-width = <4>;
+       no-sdio;
+       no-mmc;
+       wp-inverted;
+       status = "okay";
+};
+
 &uart0 {
        status = "okay";
 };
index eebd6817520e22ee2c1fd1178b97bdadd847f88b..330d297963e42d6955d5b8c28d8da2ce8d5f54ca 100644 (file)
                        resets = <&rstgen RST_UART0>;
                        status = "disabled";
                };
+
+               emmc: mmc@704002a000 {
+                       compatible = "sophgo,sg2042-dwcmshc";
+                       reg = <0x70 0x4002a000 0x0 0x1000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clkgen GATE_CLK_EMMC_100M>,
+                                <&clkgen GATE_CLK_AXI_EMMC>,
+                                <&clkgen GATE_CLK_100K_EMMC>;
+                       clock-names = "core",
+                                     "bus",
+                                     "timer";
+                       status = "disabled";
+               };
+
+               sd: mmc@704002b000 {
+                       compatible = "sophgo,sg2042-dwcmshc";
+                       reg = <0x70 0x4002b000 0x0 0x1000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clkgen GATE_CLK_SD_100M>,
+                                <&clkgen GATE_CLK_AXI_SD>,
+                                <&clkgen GATE_CLK_100K_SD>;
+                       clock-names = "core",
+                                     "bus",
+                                     "timer";
+                       status = "disabled";
+               };
        };
 };