struct dm_crtc_state *dm_old_crtc_state;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        struct dsc_mst_fairness_vars vars[MAX_PIPES];
-#endif
        struct drm_dp_mst_topology_state *mst_state;
        struct drm_dp_mst_topology_mgr *mgr;
+#endif
 
        trace_amdgpu_dm_atomic_check_begin(state);
 
 
        struct drm_dp_mst_topology_mgr *mst_mgr;
        struct drm_dp_mst_port *mst_port;
        bool ret;
-       u8 link_coding_cap;
+       u8 link_coding_cap = DP_8b_10b_ENCODING;
 
        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
        /* Accessing the connector state is required for vcpi_slots allocation
 
        mst_port = aconnector->port;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
        link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
+#endif
 
        if (enable) {