struct amd_powerplay {
        void *pp_handle;
        const struct amd_pm_funcs *pp_funcs;
+       uint32_t pp_feature;
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
 
                        return -EAGAIN;
        }
 
+       adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
+
        for (i = 0; i < adev->num_ip_blocks; i++) {
                if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
                        DRM_ERROR("disabled ip block: %d <%s>\n",
 
        pi->pcie_dpm_key_disabled = 0;
        pi->thermal_sclk_dpm_enabled = 0;
 
-       if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
+       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;
 
                pi->caps_tcp_ramping = true;
        }
 
-       if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
+       if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;
 
        mutex_init(&hwmgr->smu_lock);
        hwmgr->chip_family = adev->family;
        hwmgr->chip_id = adev->asic_type;
-       hwmgr->feature_mask = amdgpu_pp_feature_mask;
+       hwmgr->feature_mask = adev->powerplay.pp_feature;
        hwmgr->display_config = &adev->pm.pm_display_cfg;
        adev->powerplay.pp_handle = hwmgr;
        adev->powerplay.pp_funcs = &pp_dpm_funcs;