static void b44_halt(struct b44 *);
 static void b44_init_rings(struct b44 *);
-static void b44_init_hw(struct b44 *);
+static void b44_init_hw(struct b44 *, int);
 
 static int dma_desc_align_mask;
 static int dma_desc_sync_size;
                spin_lock_irq(&bp->lock);
                b44_halt(bp);
                b44_init_rings(bp);
-               b44_init_hw(bp);
+               b44_init_hw(bp, 1);
                netif_wake_queue(bp->dev);
                spin_unlock_irq(&bp->lock);
                done = 1;
 
        b44_halt(bp);
        b44_init_rings(bp);
-       b44_init_hw(bp);
+       b44_init_hw(bp, 1);
 
        spin_unlock_irq(&bp->lock);
 
        b44_halt(bp);
        dev->mtu = new_mtu;
        b44_init_rings(bp);
-       b44_init_hw(bp);
+       b44_init_hw(bp, 1);
        spin_unlock_irq(&bp->lock);
 
        b44_enable_ints(bp);
  * packet processing.  Invoked with bp->lock held.
  */
 static void __b44_set_rx_mode(struct net_device *);
-static void b44_init_hw(struct b44 *bp)
+static void b44_init_hw(struct b44 *bp, int full_reset)
 {
        u32 val;
 
        b44_chip_reset(bp);
-       b44_phy_reset(bp);
-       b44_setup_phy(bp);
+       if (full_reset) {
+               b44_phy_reset(bp);
+               b44_setup_phy(bp);
+       }
 
        /* Enable CRC32, set proper LED modes and power on PHY */
        bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
        bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 
        bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
-       bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
-       bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
-       bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
-                             (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
-       bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
+       if (full_reset) {
+               bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
+               bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
+               bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
+                                     (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
+               bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
 
-       bw32(bp, B44_DMARX_PTR, bp->rx_pending);
-       bp->rx_prod = bp->rx_pending;
+               bw32(bp, B44_DMARX_PTR, bp->rx_pending);
+               bp->rx_prod = bp->rx_pending;
 
-       bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
+               bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
+       } else {
+               bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
+                                     (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
+       }
 
        val = br32(bp, B44_ENET_CTRL);
        bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
                goto out;
 
        b44_init_rings(bp);
-       b44_init_hw(bp);
+       b44_init_hw(bp, 1);
 
        b44_check_phy(bp);
 
        netif_poll_enable(dev);
 
        if (bp->flags & B44_FLAG_WOL_ENABLE) {
-               b44_init_hw(bp);
+               b44_init_hw(bp, 0);
                b44_setup_wol(bp);
        }
 
 
        b44_halt(bp);
        b44_init_rings(bp);
-       b44_init_hw(bp);
+       b44_init_hw(bp, 1);
        netif_wake_queue(bp->dev);
        spin_unlock_irq(&bp->lock);
 
        if (bp->flags & B44_FLAG_PAUSE_AUTO) {
                b44_halt(bp);
                b44_init_rings(bp);
-               b44_init_hw(bp);
+               b44_init_hw(bp, 1);
        } else {
                __b44_set_flow_ctrl(bp, bp->flags);
        }
 
        free_irq(dev->irq, dev);
        if (bp->flags & B44_FLAG_WOL_ENABLE) {
-               b44_init_hw(bp);
+               b44_init_hw(bp, 0);
                b44_setup_wol(bp);
        }
        pci_disable_device(pdev);
        spin_lock_irq(&bp->lock);
 
        b44_init_rings(bp);
-       b44_init_hw(bp);
+       b44_init_hw(bp, 1);
        netif_device_attach(bp->dev);
        spin_unlock_irq(&bp->lock);