clk: sunxi-ng: a523: remaining mod clocks

Add the remaining mod clocks, driving various parts of the SoC: the "LEDC"
LED controller, the "CSI" camera interface, the "ISP" image processor,
the DSP clock, and the "fanout" clocks, which allow to put clock signals
on external pins.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-12-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
index f62a32fa70e4e1cd57451d9a3223b2d75948a29b..0f28e453440ae321f5f4000eb5e78eeaad3788c4 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -862,6 +862,157 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0,
                                    BIT(31),    /* gate */
                                    CLK_SET_RATE_PARENT);
 
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents,
+                                     0xbf0,
+                                     0, 4,     /* M */
+                                     24, 1,    /* mux */
+                                     BIT(31),  /* gate */
+                                     0);
+
+static const struct clk_hw *csi_top_parents[] = {
+       &pll_periph0_300M_clk.hw,
+       &pll_periph0_400M_clk.hw,
+       &pll_periph0_480M_clk.common.hw,
+       &pll_video3_4x_clk.common.hw,
+       &pll_video3_3x_clk.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents,
+                                   0xc04,
+                                   0, 5,       /* M */
+                                   24, 3,      /* mux */
+                                   BIT(31),    /* gate */
+                                   0);
+
+static const struct clk_parent_data csi_mclk_parents[] = {
+       { .fw_name = "hosc" },
+       { .hw = &pll_video3_4x_clk.common.hw },
+       { .hw = &pll_video0_4x_clk.common.hw },
+       { .hw = &pll_video1_4x_clk.common.hw },
+       { .hw = &pll_video2_4x_clk.common.hw },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents,
+                                 0xc08,
+                                 0, 5,         /* M */
+                                 8, 5,         /* P */
+                                 24, 3,        /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents,
+                                 0xc0c,
+                                 0, 5,         /* M */
+                                 8, 5,         /* P */
+                                 24, 3,        /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents,
+                                 0xc10,
+                                 0, 5,         /* M */
+                                 8, 5,         /* P */
+                                 24, 3,        /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents,
+                                 0xc14,
+                                 0, 5,         /* M */
+                                 8, 5,         /* P */
+                                 24, 3,        /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static const struct clk_hw *isp_parents[] = {
+       &pll_periph0_300M_clk.hw,
+       &pll_periph0_400M_clk.hw,
+       &pll_video2_4x_clk.common.hw,
+       &pll_video3_4x_clk.common.hw,
+};
+static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0xc20,
+                                   0, 5,       /* M */
+                                   24, 3,      /* mux */
+                                   BIT(31),    /* gate */
+                                   0);
+
+static const struct clk_parent_data dsp_parents[] = {
+       { .fw_name = "hosc" },
+       { .fw_name = "losc" },
+       { .fw_name = "iosc" },
+       { .hw = &pll_periph0_2x_clk.common.hw },
+       { .hw = &pll_periph0_480M_clk.common.hw, },
+};
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
+                                     0, 5,     /* M */
+                                     24, 3,    /* mux */
+                                     BIT(31),  /* gate */
+                                     0);
+
+static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
+                          0xf30, BIT(0), 0);
+static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
+                                      0xf30, BIT(1), 2, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
+                                     pll_periph0_480M_hws,
+                                     0xf30, BIT(2), 30, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
+                                     pll_periph0_2x_hws,
+                                     0xf30, BIT(3), 48, 0);
+static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
+                                     pll_periph0_2x_hws,
+                                     0xf30, BIT(4), 24, 0);
+
+static const struct clk_parent_data fanout_27M_parents[] = {
+       { .hw = &pll_video0_4x_clk.common.hw },
+       { .hw = &pll_video1_4x_clk.common.hw },
+       { .hw = &pll_video2_4x_clk.common.hw },
+       { .hw = &pll_video3_4x_clk.common.hw },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
+                                 fanout_27M_parents, 0xf34,
+                                 0, 5,         /* div0 */
+                                 8, 5,         /* div1 */
+                                 24, 2,        /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static const struct clk_parent_data fanout_pclk_parents[] = {
+       { .hw = &apb0_clk.common.hw }
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk",
+                                 fanout_pclk_parents,
+                                 0xf38,
+                                 0, 5,         /* div0 */
+                                 5, 5,         /* div1 */
+                                 0, 0,         /* mux */
+                                 BIT(31),      /* gate */
+                                 0);
+
+static const struct clk_parent_data fanout_parents[] = {
+       { .fw_name = "losc-fanout" },
+       { .hw = &fanout_12M_clk.common.hw, },
+       { .hw = &fanout_16M_clk.common.hw, },
+       { .hw = &fanout_24M_clk.common.hw, },
+       { .hw = &fanout_25M_clk.common.hw, },
+       { .hw = &fanout_27M_clk.common.hw, },
+       { .hw = &fanout_pclk_clk.common.hw, },
+       { .hw = &fanout_50M_clk.common.hw, },
+};
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents,
+                                   0xf3c,
+                                   0, 3,       /* mux */
+                                   BIT(21),    /* gate */
+                                   0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents,
+                                   0xf3c,
+                                   3, 3,       /* mux */
+                                   BIT(22),    /* gate */
+                                   0);
+static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents,
+                                   0xf3c,
+                                   6, 3,       /* mux */
+                                   BIT(23),    /* gate */
+                                   0);
+
 /*
  * Contains all clocks that are controlled by a hardware register. They
  * have a (sunxi) .common member, which needs to be initialised by the common
@@ -936,6 +1087,23 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
        &tcon_tv0_clk.common,
        &tcon_tv1_clk.common,
        &edp_clk.common,
+       &ledc_clk.common,
+       &csi_top_clk.common,
+       &csi_mclk0_clk.common,
+       &csi_mclk1_clk.common,
+       &csi_mclk2_clk.common,
+       &csi_mclk3_clk.common,
+       &isp_clk.common,
+       &dsp_clk.common,
+       &fanout_24M_clk.common,
+       &fanout_12M_clk.common,
+       &fanout_16M_clk.common,
+       &fanout_25M_clk.common,
+       &fanout_27M_clk.common,
+       &fanout_pclk_clk.common,
+       &fanout0_clk.common,
+       &fanout1_clk.common,
+       &fanout2_clk.common,
 };
 
 static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -1031,6 +1199,23 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
                [CLK_TCON_TV0]          = &tcon_tv0_clk.common.hw,
                [CLK_TCON_TV1]          = &tcon_tv1_clk.common.hw,
                [CLK_EDP]               = &edp_clk.common.hw,
+               [CLK_LEDC]              = &ledc_clk.common.hw,
+               [CLK_CSI_TOP]           = &csi_top_clk.common.hw,
+               [CLK_CSI_MCLK0]         = &csi_mclk0_clk.common.hw,
+               [CLK_CSI_MCLK1]         = &csi_mclk1_clk.common.hw,
+               [CLK_CSI_MCLK2]         = &csi_mclk2_clk.common.hw,
+               [CLK_CSI_MCLK3]         = &csi_mclk3_clk.common.hw,
+               [CLK_ISP]               = &isp_clk.common.hw,
+               [CLK_DSP]               = &dsp_clk.common.hw,
+               [CLK_FANOUT_24M]        = &fanout_24M_clk.common.hw,
+               [CLK_FANOUT_12M]        = &fanout_12M_clk.common.hw,
+               [CLK_FANOUT_16M]        = &fanout_16M_clk.common.hw,
+               [CLK_FANOUT_25M]        = &fanout_25M_clk.common.hw,
+               [CLK_FANOUT_27M]        = &fanout_27M_clk.common.hw,
+               [CLK_FANOUT_PCLK]       = &fanout_pclk_clk.common.hw,
+               [CLK_FANOUT0]           = &fanout0_clk.common.hw,
+               [CLK_FANOUT1]           = &fanout1_clk.common.hw,
+               [CLK_FANOUT2]           = &fanout2_clk.common.hw,
        },
 };