drm/nv41/vm: fix and enable use of "real" pciegart

Hopefully fixed the tlb flush timeout issue.  Was able to observe this
condition occur occasionally, and it appears the binary driver doesn't
wait on the old condition either..

Should give 39-bit DMA addressing on the relevant chipsets.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
index 18de4c5b202f5880553096f39f0acdce0296e121..42deadca0f0ace51cbc225cede753ac1eaa3a3c3 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
@@ -78,7 +78,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
@@ -98,7 +98,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
@@ -118,7 +118,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
@@ -158,7 +158,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
@@ -178,7 +178,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
@@ -198,7 +198,7 @@ nv40_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
+               device->oclass[NVDEV_SUBDEV_VM     ] = &nv41_vmmgr_oclass;
                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
                device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
index c5486e4bffa6a73a6f906fb139a5caf956060eea..0203e1e12caaad34f4639ec3824a33d770a5d447 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
@@ -23,6 +23,7 @@
  */
 
 #include <core/gpuobj.h>
+#include <core/option.h>
 
 #include <subdev/timer.h>
 #include <subdev/vm.h>
@@ -70,7 +71,7 @@ nv41_vm_flush(struct nouveau_vm *vm)
 
        mutex_lock(&nv_subdev(priv)->mutex);
        nv_wr32(priv, 0x100810, 0x00000022);
-       if (!nv_wait(priv, 0x100810, 0x00000100, 0x00000100)) {
+       if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) {
                nv_warn(priv, "flush timeout, 0x%08x\n",
                        nv_rd32(priv, 0x100810));
        }
@@ -87,9 +88,15 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_oclass *oclass, void *data, u32 size,
                struct nouveau_object **pobject)
 {
+       struct nouveau_device *device = nv_device(parent);
        struct nv04_vmmgr_priv *priv;
        int ret;
 
+       if (!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) {
+               return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass,
+                                          data, size, pobject);
+       }
+
        ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
                                   "pciegart", &priv);
        *pobject = nv_object(priv);