drm/amd/display: Fix disabling dccg clocks

[How & Why]
Updated procedure to match hardware programming guide.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index f98aba308028baacb558f0561f21980e4ea8c24f..493c47a3d06e0a97f9bb42c7474882c72273b787 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -183,8 +183,14 @@
        type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
        type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
        type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
+       type SYMCLK32_SE0_GATE_DISABLE;\
+       type SYMCLK32_SE1_GATE_DISABLE;\
+       type SYMCLK32_SE2_GATE_DISABLE;\
+       type SYMCLK32_SE3_GATE_DISABLE;\
        type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
        type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
+       type SYMCLK32_LE0_GATE_DISABLE;\
+       type SYMCLK32_LE1_GATE_DISABLE;\
        type DPSTREAMCLK_ROOT_GATE_DISABLE;\
        type DPSTREAMCLK_GATE_DISABLE;\
        type HDMISTREAMCLK0_DTO_PHASE;\
@@ -233,6 +239,7 @@ struct dccg_registers {
        uint32_t DSCCLK2_DTO_PARAM;
        uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
        uint32_t DPSTREAMCLK_GATE_DISABLE;
+       uint32_t DCCG_GATE_DISABLE_CNTL2;
        uint32_t DCCG_GATE_DISABLE_CNTL3;
        uint32_t HDMISTREAMCLK0_DTO_PARAM;
        uint32_t DCCG_GATE_DISABLE_CNTL4;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index ea4f8e06b07ccf10caacdeb73851424cd6a9bf36..720bd35582b0779e3a8c4758751f8468eff31ac3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -121,7 +121,8 @@ static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)
                return;
        }
        if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
-               REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+               REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                       DPSTREAMCLK_GATE_DISABLE, 1,
                        DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
 }
 
@@ -130,8 +131,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
        if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
-               REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
-                               DPSTREAMCLK_ROOT_GATE_DISABLE, 0);
+               REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                               DPSTREAMCLK_ROOT_GATE_DISABLE, 0,
+                               DPSTREAMCLK_GATE_DISABLE, 0);
 
        switch (otg_inst) {
        case 0:
@@ -180,7 +182,8 @@ void dccg31_enable_symclk32_se(
        switch (hpo_se_inst) {
        case 0:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE0_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_SE0_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE0_SRC_SEL, phyd32clk,
@@ -188,7 +191,8 @@ void dccg31_enable_symclk32_se(
                break;
        case 1:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE1_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_SE1_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE1_SRC_SEL, phyd32clk,
@@ -196,7 +200,8 @@ void dccg31_enable_symclk32_se(
                break;
        case 2:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE2_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_SE2_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE2_SRC_SEL, phyd32clk,
@@ -204,7 +209,8 @@ void dccg31_enable_symclk32_se(
                break;
        case 3:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE3_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_SE3_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_SE_CNTL,
                                SYMCLK32_SE3_SRC_SEL, phyd32clk,
@@ -229,7 +235,8 @@ void dccg31_disable_symclk32_se(
                                SYMCLK32_SE0_SRC_SEL, 0,
                                SYMCLK32_SE0_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE0_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);
                break;
        case 1:
@@ -237,7 +244,8 @@ void dccg31_disable_symclk32_se(
                                SYMCLK32_SE1_SRC_SEL, 0,
                                SYMCLK32_SE1_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE1_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);
                break;
        case 2:
@@ -245,7 +253,8 @@ void dccg31_disable_symclk32_se(
                                SYMCLK32_SE2_SRC_SEL, 0,
                                SYMCLK32_SE2_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE2_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);
                break;
        case 3:
@@ -253,7 +262,8 @@ void dccg31_disable_symclk32_se(
                                SYMCLK32_SE3_SRC_SEL, 0,
                                SYMCLK32_SE3_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_SE3_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);
                break;
        default:
@@ -275,7 +285,8 @@ void dccg31_enable_symclk32_le(
        switch (hpo_le_inst) {
        case 0:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_LE0_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE0_SRC_SEL, phyd32clk,
@@ -283,7 +294,8 @@ void dccg31_enable_symclk32_le(
                break;
        case 1:
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_LE1_GATE_DISABLE, 1,
                                        SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);
                REG_UPDATE_2(SYMCLK32_LE_CNTL,
                                SYMCLK32_LE1_SRC_SEL, phyd32clk,
@@ -308,7 +320,8 @@ void dccg31_disable_symclk32_le(
                                SYMCLK32_LE0_SRC_SEL, 0,
                                SYMCLK32_LE0_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_LE0_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);
                break;
        case 1:
@@ -316,7 +329,8 @@ void dccg31_disable_symclk32_le(
                                SYMCLK32_LE1_SRC_SEL, 0,
                                SYMCLK32_LE1_EN, 0);
                if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+                       REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+                                       SYMCLK32_LE1_GATE_DISABLE, 0,
                                        SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);
                break;
        default:

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index a013a32bbaf7b775eb8a2c26aa9a328ad8a9101d..4039273872beb404c7fe2c5c1844c3a1be99068f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -66,6 +66,7 @@
        SR(DSCCLK1_DTO_PARAM),\
        SR(DSCCLK2_DTO_PARAM),\
        SR(DSCCLK_DTO_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL2),\
        SR(DCCG_GATE_DISABLE_CNTL3),\
        SR(HDMISTREAMCLK0_DTO_PARAM)