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arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 22 Jul 2022 15:11:55 +0000 (16:11 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 16 Aug 2022 07:37:02 +0000 (09:37 +0200)
commitffd882417412ea7273ae14deec77711f6df54bbc
tree9aa4d3af2fe3fb0e4e23eb11e37f04c0775b3365tree
parent80c4ece67b4050559e4e2417e77bbfd57e8b3899commit | diff
arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
and ETH1 respectively.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi diff | blob | history
XArray, radix tree and IDR